Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay

[Mayuri Tendulkar]

Hi Zoran

Currently we are using FSP 3. But it works fine with seabios payload.

Only when I include UEFI, I am getting this issue. So I am not sure if this is related to FSP3 or 4.

My query is there any additional configurations required in UEFI Payload to make it work for Minnowboard max.

I see difference in addresses for UEFI and Seabios payload. Not sure where are they set.

Seabios payload (working)

CBFS provider active.
CBFS @ 500000 size 2ff9c0
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 76b40 size f782
'fallback/payload' located at offset: 576b78 size: f782
Loading segment from rom address 0xffd76b78
  code (compression=1)
  New segment dstaddr 0xe2780 memsize 0x1d880 srcaddr 0xffd76bb0 filesize 0xf74a
Loading segment from rom address 0xffd76b94
  Entry Point 0x000ff06e
Payload being loaded below 1MiB without region being marked as RAM usable.
Bounce Buffer at 7ac50000, 451744 bytes
Loading Segment: addr: 0x00000000000e2780 memsz: 0x000000000001d880 filesz: 0x000000000000f74a
lb: [0x0000000000100000, 0x0000000000137250)
Post relocation: addr: 0x00000000000e2780 memsz: 0x000000000001d880 filesz: 0x000000000000f74a
using LZMA
[ 0x000e2780, 00100000, 0x00100000) <- ffd76bb0
dest 000e2780, end 00100000, bouncebuffer 7ac50000
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 130526 exit 0
FspNotify(EnumInitPhaseReadyToBoot)
fsp_header_ptr: fffc0094
FSP Header Version: 1
FSP Revision: 3.3
Returned from FspNotify(EnumInitPhaseReadyToBoot)
POST: 0x7b
Jumping to boot code at 000ff06e(7acbf000)
POST: 0xf8
CPU0: stack: 0012e000 - 0012f000, lowest used address 0012eb10, stack used: 1264 bytes
entry    = 0x000ff06e
lb_start = 0x00100000
lb_size  = 0x00037250
buffer   = 0x7ac50000
SeaBIOS (version rel-1.9.0-127-gc8e105a)

UEFI Payload logs (not working)

CBFS provider active.
CBFS @ 500000 size 2ff9c0
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 56ec0 size 90b92
'fallback/payload' located at offset: 556ef8 size: 90b92
Loading segment from rom address 0xffd56ef8
  code (compression=1)
  New segment dstaddr 0x800000 memsize 0x410000 srcaddr 0xffd56f30 filesize 0x90b5a
Loading segment from rom address 0xffd56f14
  Entry Point 0x008002c0
Bounce Buffer at 7ac34000, 437408 bytes
Loading Segment: addr: 0x0000000000800000 memsz: 0x0000000000410000 filesz: 0x0000000000090b5a
lb: [0x0000000000100000, 0x0000000000135650)
Post relocation: addr: 0x0000000000800000 memsz: 0x0000000000410000 filesz: 0x0000000000090b5a
using LZMA
[ 0x00800000, 00c10000, 0x00c10000) <- ffd56f30
dest 00800000, end 00c10000, bouncebuffer 7ac34000
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0
FspNotify(EnumInitPhaseReadyToBoot)
fsp_header_ptr: fffc0094
FSP Header Version: 1
FSP Revision: 3.3
Returned from FspNotify(EnumInitPhaseReadyToBoot)
POST: 0x7b
Jumping to boot code at 008002c0(7ac9f000)
POST: 0xf8
CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack used: 1264 bytes
entry    = 0x008002c0
lb_start = 0x00100000
lb_size  = 0x00035650
buffer   = 0x7ac34000

From: Zoran Stojsavljevic [mailto:[e-mail]]
Sent: 20 May 2016 10:44
To: Mayuri Tendulkar ; coreboot 
Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay

Hello Mayuri,

If I am not mistaken (I often mix BYT Coreboot @ threads in my head), you are using BYT FSP Version 3.
> fsp_header_ptr: fffc0094 <== correct
> FSP Header Version: 1
> FSP Revision: 3.3 <== please, use Version 4

Please, try to use the latest public BYT FSP Version 4 posted at: www.intel.com/fsphttp://www.intel.com/fsp

BAYTRAIL_FSP_GOLD_004_22-MAY-2015.fd
BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG.fd

Don't remember deltas between V3 and V4, I thing something was wrong in V3 with MTRRs' setup, if I do not mix data in my head.

INTEL also has Version 5 for a quite some time, but this one for some reasons never got publicly released.

Please, report if this solved your problems.

Zoran

On Wed, May 18, 2016 at 6:56 AM, Mayuri Tendulkar <[e-mail]> wrote:
Hi

While booting my Minnomboard with coreboot and UEFI, it hangs at below point while loading the payload.

I followed the procedure to download latest EDK2 tree and built UEFIPAYLOAD.fd and copied it to coreboot/payloads/external/tianocore folder and gave this path in make menuconfig.

Has anybody come across this?

BS: BS_PAYLOAD_LOAD times (us): entry 0 run 507070 exit 0
FspNotify(EnumInitPhaseReadyToBoot)
fsp_header_ptr: fffc0094
FSP Header Version: 1
FSP Revision: 3.3
Returned from FspNotify(EnumInitPhaseReadyToBoot)
POST: 0x7b
Jumping to boot code at 008002c0(7ac9f000)
POST: 0xf8
CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cb10, stack used: 1264 bytes
entry    = 0x008002c0
lb_start = 0x00100000
lb_size  = 0x00035650
buffer   = 0x7ac34000

Regards
Mayuri
From: Mayuri Tendulkar
Sent: 17 May 2016 14:13
To: 'Zoran Stojsavljevic' <[e-mail]>; [e-mail]
Subject: RE: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay

Hi Zoran and Martin

Today I was able to build UEFIPAYLOAD separately. I included .fd file while building coreboot.rom.

But while booting, getting some errors , so debugging those.

Need to check what more customizations to be done in UEFI for Minnowmax.

Has anybody tried it?

Regards
Mayuri

From: Zoran Stojsavljevic [mailto:[e-mail]]
Sent: 16 May 2016 21:04
To: Mayuri Tendulkar <[e-mail]>; [e-mail]
Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay

OK, Mayuri,

You brought an interesting point. And this point is to be not only investigated by you, rather also by me and, perhaps, Coreboot community.

Since here, in Bayern/Deutschland is Holiday Day, I went to buy a beer in Munchen HBf, and while walking there I was thinking about your use case. Thinking deeper.

I know that you are using some INTEL CPU/SoC (do not remember which one, if you said one). But, while recapping how BIOS looks like, I did notice that SEC and PEI phases have nothing to do with UEFI EDK2. EDK 2 comes to play in DXE phase, where EDK2 actually takes place/overtakes control...

It says to me one major thing I did not notice while ago: that ARM SoCs are also eligible to run on UEFI compliant OSes, namely WIN 8.1+ (including WIN 10 and WIN 10 Athens/RT WIN 10). Which makes very interesting IOT case namely for ARM, allowing it also to compete in WIN space.

Interestingly enough, this idea did not come to my mind till few hours ago... I guess, Vincent (Zimmer) already thought about that. ;-)
_______

Martin (Roth) just replied, to solve this immediate mystery. probably for the beginning only for INTEL SoCs, but, I really hope, ARM will also integrate in this concept seamlessly! :-)

Zoran
_______

On Mon, May 16, 2016 at 2:29 PM, Mayuri Tendulkar <[e-mail]> wrote:
Hi Zoran

I have checked that site and downloaded EDK2 code. I am trying to build it on Linux but facing some issues.
But if I generate payload file separately, I need to integrate it in coreboot separately.

So I am checking if there is way to build the payload in coreboot itself.

Regards
Mayuri

From: Zoran Stojsavljevic [mailto:[e-mail]]
Sent: 16 May 2016 17:57
To: Mayuri Tendulkar <[e-mail]>
Cc: [e-mail]
Subject: Re: [coreboot] UEFI Payload in coreboot for Intel Minnowboard or Bayley bay

Hello Mayuri,

You should check payload called: Tiano Core (true UEFI payload).

Zoran

On Mon, May 16, 2016 at 2:12 PM, Mayuri Tendulkar <[e-mail]> wrote:
Hi

Is there any mechanism to build UEFI payload directly in coreboot similar like seabios?

Regards
Mayuri
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