Building Televideo/TC7010 on Fedora 12

[Peter Bannis]

Hi,

My last successful build for the Televideo/TC7010  was r3147.  The TC7010
differs little from the TC7020.  I have put in some hours trying to figure
out why but no success yet.  The changes I have noticed :

CBFS
Changes in crt0_includes.h where  failover and auto.inc ( romstage.inc )
are called after cpu and south bridge initialisation.
romcc generates wrong code in pc97317_early_serial_init.c
    /* Wait for the clock to stabilise */
     while(!inb(PM_BASE + 1 & 0x80))
              ;

L1024:
 595                      /* ,:0.0 */
 596                      /*
 597                       * __builtin_inb,<built-in>:1.0
 598                       * inb,io.h:31.29
 599                       *
pc97317_enable_serial,pc97317_early_serial.c:44.19
 600                       * main,romstage.c:43.30
 601                       */
 602 02db E480             inb  $128 , %al
 603 02dd 0FB6E8           movzx %al, %ebp
 604                      /*
 605                       *
pc97317_enable_serial,pc97317_early_serial.c:44.39
 606                       * main,romstage.c:43.30
 607                       */
 608 02e0 85ED             test %ebp, %ebp
 609 02e2 74F7             jz L1024

We really want to test the high bit of index reg 0x03 at port 0xe8 for clock
stability.

This is not the problem however as the same code was generated in r3147.

can someone send me a rom image for the Televideo/TC7020 latest build that
way I'd know I need to change my platform or patch the r3147 rom to follow
the same initialization sequence.

All ideas welcomed!

peterBE

[ron minnich]

On Sat, Feb 13, 2010 at 10:36 AM, Peter Bannis  wrote:
> romcc generates wrong code in pc97317_early_serial_init.c
>     /* Wait for the clock to stabilise */
>      while(!inb(PM_BASE + 1 & 0x80))
>               ;

Should this be
while(!(inb(PM_BASE + 1) & 0x80))

or some such? You're doing an inb from PM_BASE+1&0x80 as an address?
I'm confused.

ron

[Peter Bannis]

You are not confused.  It should be
  while(!(inb(PM_BASE + 1) & 0x80))

but the current code has
while(!inb(PM_BASE + 1 & 0x80))

either way incorrect code to read port 0x80 is generated instead of reads to
port (0xe8+1):
L1024:
        /* ,:0.0 */
        /*
         * __builtin_inb,<built-in>:1.0
         * inb,io.h:31.29
         * pc97317_enable_serial,pc97317_early_serial.c:44.19
         * main,romstage.c:43.30
         */
        inb  $128 , %al
        movzx %al, %ebp
        /*
         * pc97317_enable_serial,pc97317_early_serial.c:44.39
         * main,romstage.c:43.30
         */
        test %ebp, %ebp
        jz L1024
.

On Sun, Feb 14, 2010 at 3:05 AM, ron minnich  wrote:
> On Sat, Feb 13, 2010 at 10:36 AM, Peter Bannis 
> wrote:
> > romcc generates wrong code in pc97317_early_serial_init.c
> >     /* Wait for the clock to stabilise */
> >      while(!inb(PM_BASE + 1 & 0x80))
> >               ;
>
> Should this be
> while(!(inb(PM_BASE + 1) & 0x80))
>
> or some such? You're doing an inb from PM_BASE+1&0x80 as an address?
> I'm confused.
>
> ron

[Stefan Reinauer]

On 2/14/10 11:02 PM, Peter Bannis wrote:
> You are not confused. It should be
> while(!(inb(PM_BASE + 1) & 0x80))
>
> but the current code has
> while(!inb(PM_BASE + 1 & 0x80))
>
> either way incorrect code to read port 0x80 is generated instead of
> reads to port (0xe8+1):

Not here. You should probably clean your output directory and start fresh.

Stefan