Re: [coreboot] Strange postcodes

[Patrick Rudolph]

Hi.
Most post codes use pre defined values instead of hardcoded values ( src/include/console/post_codes.h) . Sadly there's no documentation of possible post codes, as it's board specific.
Binary blobs, like Intel mrc.bin, have their own 16bit post code set.
Asm code is of course sending post codes to, and of course it's not using any c function to do so.
Regards, Patrick

Am 7. August 2016 10:11:32 MESZ, schrieb "Łukasz Dobrowolski" :
> Hello!
> I'm porting cb to ThinkPad X120e. I've used code from asrock/e350m1 as
> basis and made some small changes.
>
> I'm getting following postcodes. Those are after "50" so romstage.c
> finished executing. (System sometimes goes this far, other times it
> hangs earlier.)
>        79 24 98 7A A8 F8
>
> I tried to find them in like this:
>        grep -R 'post_code(0x24);'
> I've only found "24", it's in device/pci_device.c:1113. Whatever is
> sending the rest of the postcodes is not using post_code() function.
>
> I can think of 3 explanations:
>        Payload is sending those postcodes. -> Seams unlikely, I'm
> using Seabios. I've read some of the code and can't find any places
> that would send the codes.
>        ASM parts of cb/AGESA.
>        EC(ITE IT8518E) is sending the codes.
>
> Any thoughts?