[PATCH] fix K8M890

[Rudolf Marek]

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Hello

Attached patch fixes at least one issue ;) During the PCI BAR sizing must be the
D1F0 bridge without activated I/O and MEM resources, otherwise it will hang
whole PCI bus.

U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why
does we not.

Second small change just changes a bit which controls the PSTATECTL logic.

Signed-off-by: Rudolf Marek

Rudolf
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[Rudolf Marek]

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Hello all,

Here comes some updated patch:

Attached patch fixes at least one issue ;) During the PCI BAR sizing must be the
 D1F0 bridge without activated I/O and MEM resources, otherwise it will hang
 whole PCI bus.

U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why
 does we not.

Second small change just changes a bit which controls the PSTATECTL logic.

Third change deals with the integrated VGA, which needs to be enabled early,
 so the VGA_EN is set along the bridges, and PCI K8 resource maps are set
 correctly. Finally the CPU accessible framebuffer is now disabled as it is not
 needed.

Signed-off-by: Rudolf Marek

Rudolf
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[Carl-Daniel Hailfinger]

On 16.09.2008 00:04, Rudolf Marek wrote:
> Attached patch fixes at least one issue ;) During the PCI BAR sizing
> must be the
>  D1F0 bridge without activated I/O and MEM resources, otherwise it
> will hang
>  whole PCI bus.
>
> U-boot is also disabling the IO/MEM decode when sizing the BARs, dont
> know why
>  does we not.
>
> Second small change just changes a bit which controls the PSTATECTL
> logic.
>
> Third change deals with the integrated VGA, which needs to be enabled
> early,
>  so the VGA_EN is set along the bridges, and PCI K8 resource maps are set
>  correctly. Finally the CPU accessible framebuffer is now disabled as
> it is not
>  needed.
>
> Signed-off-by: Rudolf Marek

The old code had some obvious problems and the new code looks better.

Acked-by: Carl-Daniel Hailfinger

One question about the following snippet, though:
> /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */
> tmp = pci_read_config8(dev, PCI_COMMAND);
> tmp &= ~0x3;
> pci_write_config8(dev, PCI_COMMAND, tmp);

AFAICS that's a workaround for a hardware bug (more explanations in code
comments welcome). Do you reenable I/O and memory decode after BAR sizing?

Regards,
Carl-Daniel

[Rudolf Marek]

It seems like hw bug, but I think we should change PCI BAR probing and disable 
the regions before probing and restore them later to original values, same as 
U-boot does.
> One question about the following snippet, though:
> > /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */
> > tmp = pci_read_config8(dev, PCI_COMMAND);
> > tmp &= ~0x3;
> > pci_write_config8(dev, PCI_COMMAND, tmp);
>
> AFAICS that's a workaround for a hardware bug (more explanations in code
> comments welcome). Do you reenable I/O and memory decode after BAR sizing?

Nope, because integrated VGA has no other then legacy ports. Second reason is 
that if there would be some IO resources, the set resources would enable the 
bridge anyway.

Thanks,
Rudolf