Cache aliasing - coreboot

8 Apr 2009


      Hi,
I wanted to investigate the possibility of CAR usage for older Intel
processors, thereby reducing ROMCC usage and compilation time
substantially. However, there are some properties of caches I'd like to
understand better.
The following article is what I'm basing my questions on:
http://www.linuxjournal.com/article/7105
Please fact-check the following sentences and point out if they contain
any errors. Thanks.
As long as cache lines are not evicted or invalidated, it should be safe
to use the address range they are covering for CAR. Their content may be
written to memory, but their content will not be fetched from memory.
Eviction of a given line A can only happen if the processor reads from a
memory location having the same cache index as A but an address
differing from A. This is called aliasing.
Thus, by making sure no two memory locations with the same cacheline
index are cacheable, eviction will not happen.
The formula to determine the minimum distance between aliasing addresses is
cachelinesize*2^indexlength
For n-way associative caches, the minimum distance between aliasing
addresses is
associativityways*cachelinesize*2^indexlength
if you make sure that no more than n memory ranges (each with cache line
size) with the same index are marked as cacheable.
Invalidation only happens on WBINVD, INVD and CLFLUSH. Hardware outside
the CPU may trigger invalidation as well.
If all of the above is true, it should be possible to use CAR on every
processor which has a fine-grained memory range cache control like MTRR.
Simply make sure the cacheable area is smaller than cache size and
smaller than the minimum aliasing distance, switch caches on and be
happy. (External hardware may need to be told it should not trigger
invalidation.)
Is it really that easy?
Regards,
Carl-Daniel
-- 
http://www.hailfinger.org/