Hi, We are developing coreboot along with UEFI shell payload for Coffelake architecture. We are using the processor integrated graphics controller for display.
I am getting the following error on porting the coreboot. Grahics hand-off block not found.FSP did not return a valid framebuffer. I checked internal graphics is enabled in FSP and graphics memory is set to 32 MB. Also applied a patch found in coreboot mailing list on device tree and gpio files for Intel graphics. Whether Coreboot can print any messages on the display (other than console).
Coreboot came up and I got the shell prompt on Uart Console. The same shell prompt has to come on the display (monitor) but not displayed. I suspect some graphics initialization problem.
Regards,gsen.
FSP can't initialize the graphics device without a valid VBT being loaded. Are you supplying that and setting the associated options in your config?
On Fri, Oct 4, 2019, 12:32 AM Senthil Kumar G via coreboot < coreboot@coreboot.org> wrote:
Hi,
We are developing coreboot along with UEFI shell payload for Coffelake architecture. We are using the processor integrated graphics controller for display.
I am getting the following error on porting the coreboot.
Grahics hand-off block not found. FSP did not return a valid framebuffer.
I checked internal graphics is enabled in FSP and graphics memory is set to 32 MB. Also applied a patch found in coreboot mailing list on device tree and gpio files for Intel graphics.
Whether Coreboot can print any messages on the display (other than console).
Coreboot came up and I got the shell prompt on Uart Console. The same shell prompt has to come on the display (monitor) but not displayed. I suspect some graphics initialization problem.
Regards, gsen.
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Hi, I have added the VBT in the coreboot. CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/intel/cflrvp/VbtCfl_h.bin" On Friday, 4 October, 2019, 11:26:19 am IST, Matt DeVillier matt.devillier@gmail.com wrote:
FSP can't initialize the graphics device without a valid VBT being loaded. Are you supplying that and setting the associated options in your config? On Fri, Oct 4, 2019, 12:32 AM Senthil Kumar G via coreboot coreboot@coreboot.org wrote:
Hi, We are developing coreboot along with UEFI shell payload for Coffelake architecture. We are using the processor integrated graphics controller for display.
I am getting the following error on porting the coreboot. Grahics hand-off block not found.FSP did not return a valid framebuffer. I checked internal graphics is enabled in FSP and graphics memory is set to 32 MB. Also applied a patch found in coreboot mailing list on device tree and gpio files for Intel graphics. Whether Coreboot can print any messages on the display (other than console).
Coreboot came up and I got the shell prompt on Uart Console. The same shell prompt has to come on the display (monitor) but not displayed. I suspect some graphics initialization problem.
Regards,gsen.
_______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
_______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Hi, I have added the wrong VBT file. Corrected it and display is coming. Is there any way to configure all uart of the processor. I am getting only one serial controller in list of lspci. Coffeelake has three uart ports but only one is getting listed. Thanks for the support.
rgds,gsen
On Friday, 4 October, 2019, 12:18:49 pm IST, Senthil Kumar G via coreboot coreboot@coreboot.org wrote:
Hi, I have added the VBT in the coreboot. CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/intel/cflrvp/VbtCfl_h.bin" On Friday, 4 October, 2019, 11:26:19 am IST, Matt DeVillier matt.devillier@gmail.com wrote:
FSP can't initialize the graphics device without a valid VBT being loaded. Are you supplying that and setting the associated options in your config? On Fri, Oct 4, 2019, 12:32 AM Senthil Kumar G via coreboot coreboot@coreboot.org wrote:
Hi, We are developing coreboot along with UEFI shell payload for Coffelake architecture. We are using the processor integrated graphics controller for display.
I am getting the following error on porting the coreboot. Grahics hand-off block not found.FSP did not return a valid framebuffer. I checked internal graphics is enabled in FSP and graphics memory is set to 32 MB. Also applied a patch found in coreboot mailing list on device tree and gpio files for Intel graphics. Whether Coreboot can print any messages on the display (other than console).
Coreboot came up and I got the shell prompt on Uart Console. The same shell prompt has to come on the display (monitor) but not displayed. I suspect some graphics initialization problem.
Regards,gsen.
_______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
_______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Dear Senthil,
On 2019-10-04 16:19, Senthil Kumar G via coreboot wrote:
Is there any way to configure all uart of the processor. I am getting only one serial controller in list of lspci. Coffeelake has three uart ports but only one is getting listed.
Please start a separate thread by that, by creating a new message (no reply-to), and with a descriptive and appropriate subject, cf [1] for example.
Kind regards,
Paul
[1]: https://en.opensuse.org/openSUSE:Mailing_list_netiquette
Hi,
Search your devicetree.cb for UART PCI devices like:
device pci 19.2 on end # UART #2 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1
As you can see above these entries describe the device.function of the UART and the on/off switch. Try to turn them on and see what happens. Additionally you will have to have an array defining SerialIO devices in devicetree like:
register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSPI0] = PchSerialIoPci, [PchSerialIoIndexSPI1] = PchSerialIoPci, [PchSerialIoIndexSPI2] = PchSerialIoDisabled, [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" So it will pass the correct parameters to FSP. You have to either choose PchSerialIoPci or PchSerialIoAcpi, depending on your needs.
Regards, Michał
On 04.10.2019 16:19, Senthil Kumar G via coreboot wrote:
Hi,
I have added the wrong VBT file. Corrected it and display is coming.
Is there any way to configure all uart of the processor. I am getting only one serial controller in list of lspci. Coffeelake has three uart ports but only one is getting listed.
Thanks for the support.
rgds, gsen
On Friday, 4 October, 2019, 12:18:49 pm IST, Senthil Kumar G via coreboot coreboot@coreboot.org wrote:
Hi,
I have added the VBT in the coreboot.
CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/intel/cflrvp/VbtCfl_h.bin"
On Friday, 4 October, 2019, 11:26:19 am IST, Matt DeVillier matt.devillier@gmail.com wrote:
FSP can't initialize the graphics device without a valid VBT being loaded. Are you supplying that and setting the associated options in your config?
On Fri, Oct 4, 2019, 12:32 AM Senthil Kumar G via coreboot <coreboot@coreboot.org mailto:coreboot@coreboot.org> wrote:
Hi, We are developing coreboot along with UEFI shell payload for Coffelake architecture. We are using the processor integrated graphics controller for display. I am getting the following error on porting the coreboot. Grahics hand-off block not found. FSP did not return a valid framebuffer. I checked internal graphics is enabled in FSP and graphics memory is set to 32 MB. Also applied a patch found in coreboot mailing list on device tree and gpio files for Intel graphics. Whether Coreboot can print any messages on the display (other than console). Coreboot came up and I got the shell prompt on Uart Console. The same shell prompt has to come on the display (monitor) but not displayed. I suspect some graphics initialization problem. Regards, gsen. _______________________________________________ coreboot mailing list -- coreboot@coreboot.org <mailto:coreboot@coreboot.org> To unsubscribe send an email to coreboot-leave@coreboot.org <mailto:coreboot-leave@coreboot.org>
coreboot mailing list -- coreboot@coreboot.org mailto:coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org mailto:coreboot-leave@coreboot.org _______________________________________________ coreboot mailing list -- coreboot@coreboot.org mailto:coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org mailto:coreboot-leave@coreboot.org
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Hi,
On Fri, Oct 4, 2019, 16:39 Michal Zygowski michal.zygowski@3mdeb.com wrote:
Hi,
Search your devicetree.cb for UART PCI devices like:
device pci 19.2 on end # UART #2 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1
As you can see above these entries describe the device.function of the UART and the on/off switch. Try to turn them on and see what happens. Additionally you will have to have an array defining SerialIO devices in devicetree like:
register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSPI0] = PchSerialIoPci, [PchSerialIoIndexSPI1] = PchSerialIoPci, [PchSerialIoIndexSPI2] = PchSerialIoDisabled, [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }"So it will pass the correct parameters to FSP. You have to either choose PchSerialIoPci or PchSerialIoAcpi, depending on your needs.
I would also recommend checking if the PCH GPIO configuration values are correct. In src/mainboard/vendor/model there should be a file called either 'gpio.c' or 'gpio.h', which is used to configure the function of GPIO pins.
To use the UART function, the relevant pins (balls, rather) should be configured as "Native" function. GPIO ball numbers and functions can be found in the PCH datasheet.
Regards, Michał
-- Michał Żygowski Firmware Engineerhttp://3mdeb.com | @3mdeb_com
Best regards,
Angel Pons
-
Angel Pons -
Matt DeVillier -
Michal Zygowski -
Paul Menzel -
Senthil Kumar G