r776 - in coreboot-v3: mainboard/amd/serengeti southbridge/amd/amd8111

Author: rminnich
Date: 2008-08-16 04:34:51 +0200 (Sat, 16 Aug 2008)
New Revision: 776

Modified:
   coreboot-v3/mainboard/amd/serengeti/Makefile
   coreboot-v3/mainboard/amd/serengeti/initram.c
   coreboot-v3/southbridge/amd/amd8111/stage1_ctrl.c
   coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c
Log:
This gets closer to building serengeti. The next step is to go back and flush out all the 
issues in k8 north.

Signed-off-by: Ronald G. Minnich 
Acked-by: Ronald G. Minnich

Modified: coreboot-v3/mainboard/amd/serengeti/Makefile
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/Makefile	2008-08-16 00:10:25 UTC (rev 775)
+++ coreboot-v3/mainboard/amd/serengeti/Makefile	2008-08-16 02:34:51 UTC (rev 776)
@@ -22,8 +22,10 @@
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o \
    		$(obj)/mainboard/$(MAINBOARDDIR)/option_table.o \
    		$(obj)/southbridge/amd/amd8111/stage1_smbus.o \
+			$(obj)/southbridge/amd/amd8111/stage1_ctrl.o \
    		$(obj)/northbridge/amd/k8/coherent_ht.o \
    		$(obj)/northbridge/amd/k8/incoherent_ht.o \
+			$(obj)/northbridge/amd/k8/libstage1.o \
    		$(obj)/lib/clog2.o

INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \

Modified: coreboot-v3/mainboard/amd/serengeti/initram.c
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/initram.c	2008-08-16 00:10:25 UTC (rev 775)
+++ coreboot-v3/mainboard/amd/serengeti/initram.c	2008-08-16 02:34:51 UTC (rev 776)
@@ -31,7 +31,6 @@
 #include <io.h>
 #include <cpu.h>
 #include <amd/k8/k8.h>
-#include <southbridge/nvidia/mcp55/mcp55_smbus.h>
 #include <mc146818rtc.h>
 #include <spd.h>

Modified: coreboot-v3/southbridge/amd/amd8111/stage1_ctrl.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/stage1_ctrl.c	2008-08-16 00:10:25 UTC (rev 775)
+++ coreboot-v3/southbridge/amd/amd8111/stage1_ctrl.c	2008-08-16 02:34:51 UTC (rev 776)
@@ -23,19 +23,22 @@
 #include <device/pci.h>
 #include <msr.h>
 #include <legacy.h>
-#include <device/pci_ids.h>
+#include <device/pci.h>
 #include <statictree.h>
 #include <config.h>
+#include <io.h>
 #include "amd8111.h"

-
+void set_bios_reset(void);
+unsigned get_sblk(void);
+u8 get_sbbusn(unsigned int sblk);
 /* by yhlu 2005.10 */
 /** 
  * Get the device fn for the 8111. 
  * @param bus the bus on which to search
  * @return The device number, in the range 0-31
  */
-static u32 get_sbdn(unsigned bus)
+u32 get_sbdn(unsigned bus)
 {
         u32 dev;

@@ -45,11 +48,8 @@

pci_conf1_find_on_bus(bus, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI, &dev);

-	/* this makes no sense. At all. I wonder if this is an ancient bug. >> 15? */
-#warning shift right 15? makes no sense. 
+        return (dev>>11) & 0x1f;

-        return (dev>>15) & 0x1f;
-
 }

/** 
@@ -57,7 +57,7 @@
  * @param bus the bus on which to search
  * @return The device number, in the range 0-31
  */
-static void enable_cf9_x(unsigned sbbusn, unsigned sbdn)
+void enable_cf9_x(unsigned sbbusn, unsigned sbdn)
 {
    u32 dev;
    u8 byte;
@@ -66,13 +66,13 @@
    /* enable cf9 */
    byte = pci_conf1_read_config8(dev, 0x41);
    byte |= (1<<6) | (1<<5);
-	pci_conf1+write_config8(dev, 0x41, byte);
+	pci_conf1_write_config8(dev, 0x41, byte);
 }

/** 
  * Enable "cf9". cf9 is a commonly used 8-bit IO address for reset, overlapping the 32-bit cf8 config address. 
  */
-static void enable_cf9(void)
+void enable_cf9(void)
 {
    u32 sblk = get_sblk();
    u32 sbbusn = get_sbbusn(sblk);
@@ -86,7 +86,7 @@
  * came out of a coreboot-initiated reset. 
  * @return Never returns. 
  */
-static void hard_reset(void)
+void hard_reset(void)
 {
         set_bios_reset();
         /* reset */
@@ -99,7 +99,7 @@
  * @param sbbusn south bridge bus number
  * @param sbdn southbridge device numer 
  */
-static void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn)
+void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn)
 {
    u32 dev;

@@ -118,7 +118,7 @@
  * @param sbdn southbridge device numer 
  * @return never
  */
-static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
+void soft_reset_x(unsigned sbbusn, unsigned sbdn)
 {
         u32 dev;

@@ -134,7 +134,7 @@
  * Initiate a soft reset by finding the southbridge and calling soft_reset_x
  * @return never
  */
-static void soft_reset(void)
+void soft_reset(void)
 {

unsigned sblk = get_sblk();

Modified: coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c	2008-08-16 00:10:25 UTC (rev 775)
+++ coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c	2008-08-16 02:34:51 UTC (rev 776)
@@ -288,3 +288,20 @@
    return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
 }

+/**
+ * Read a byte from the SPD.
+ *
+ * For this chip, that is really just saying 'read a byte from SMBus'.
+ * So we use smbus_read_byte(). Nota Bene: leave this here as a function
+ * rather than a #define in an obscure location. This function is called
+ * only a few dozen times, and it's not performance critical.
+ *
+ * @param device The device.
+ * @param address The address.
+ * @return The data from the SMBus packet area or an error of 0xff (i.e. -1).
+ */
+u8 spd_read_byte(u16 device, u8 address)
+{
+        return smbus_read_byte(device, address);
+}
+