r782 - in coreboot-v3: arch/x86 lib mainboard/adl/msm800sev mainboard/amd/db800 mainboard/amd/norwich mainboard/amd/serengeti mainboard/artecgroup/dbe61 mainboard/artecgroup/dbe62 mainboard/emulation/qemu-x86 mainboard/gigabyte/m57sli mainboard/pcengines/alix1c mainboard/pcengines/alix2c3 southbridge/amd/amd8111 southbridge/amd/cs5536 southbridge/nvidia/mcp55 superio/fintek/f71805f superio/ite/it8716f superio/winbond/w83627hf
Author: hailfinger Date: 2008-08-18 13:15:43 +0200 (Mon, 18 Aug 2008) New Revision: 782
Modified: coreboot-v3/arch/x86/Makefile coreboot-v3/lib/Makefile coreboot-v3/mainboard/adl/msm800sev/Makefile coreboot-v3/mainboard/amd/db800/Makefile coreboot-v3/mainboard/amd/norwich/Makefile coreboot-v3/mainboard/amd/serengeti/Makefile coreboot-v3/mainboard/artecgroup/dbe61/Makefile coreboot-v3/mainboard/artecgroup/dbe62/Makefile coreboot-v3/mainboard/emulation/qemu-x86/Makefile coreboot-v3/mainboard/gigabyte/m57sli/Makefile coreboot-v3/mainboard/pcengines/alix1c/Makefile coreboot-v3/mainboard/pcengines/alix2c3/Makefile coreboot-v3/southbridge/amd/amd8111/Makefile coreboot-v3/southbridge/amd/cs5536/Makefile coreboot-v3/southbridge/nvidia/mcp55/Makefile coreboot-v3/superio/fintek/f71805f/Makefile coreboot-v3/superio/ite/it8716f/Makefile coreboot-v3/superio/winbond/w83627hf/Makefile Log: Change v3 makefile rules to be source-based, part I. The individual makefiles in lib/ mainboard/ southbridge/ and superio/ have been changed accordingly and the big glue layer in arch/x86Makefile has been modified to wrap the new rules correctly.
This pepares the way for additional optimizations during compile and link time.
Build tested and boot tested on Qemu.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/arch/x86/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -3,6 +3,7 @@ ## ## Copyright (C) 2006-2007 coresystems GmbH ## (Written by Stefan Reinauer stepan@coresystems.de for coresystems GmbH) +## Copyright (C) 2007-2008 Carl-Daniel Hailfinger ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -98,15 +99,15 @@ #
-STAGE0_LIB_OBJ = uart8250.o mem.o lar.o delay.o vtxprintf.o \ - vsprintf.o console.o string.o $(DECOMPRESSORS) -STAGE0_ARCH_X86_OBJ = stage1.o serial.o speaker.o \ - udelay_io.o mc146818rtc.o post_code.o \ - pci_ops_conf1.o resourcemap.o +STAGE0_LIB_SRC = uart8250.c mem.c lar.c delay.c vtxprintf.c \ + vsprintf.c console.c string.c $(DECOMPRESSORS) +STAGE0_ARCH_X86_SRC = stage1.c serial.c speaker.c \ + udelay_io.c mc146818rtc.c post_code.c \ + pci_ops_conf1.c resourcemap.c
ifeq ($(CONFIG_PAYLOAD_ELF_LOADER),y) -STAGE0_LIB_OBJ += elfboot.o -STAGE0_ARCH_X86_OBJ += archelfboot.o +STAGE0_LIB_SRC += elfboot.c +STAGE0_ARCH_X86_SRC += archelfboot.c endif
ifeq ($(CONFIG_CPU_I586),y) @@ -114,12 +115,12 @@ else ifeq ($(CONFIG_CPU_AMD_GEODELX),y) STAGE0_CAR_OBJ = geodelx/stage0.o - STAGE0_ARCH_X86_OBJ += geodelx/stage1.o - STAGE0_ARCH_X86_OBJ += ../../northbridge/amd/geodelx/geodelxinit.o + STAGE0_ARCH_X86_SRC += geodelx/stage1.c + STAGE0_ARCH_X86_SRC += ../../northbridge/amd/geodelx/geodelxinit.c else ifeq ($(CONFIG_CPU_AMD_K8),y) STAGE0_CAR_OBJ = amd/stage0.o - STAGE0_ARCH_X86_OBJ += amd/k8/stage1.o + STAGE0_ARCH_X86_SRC += amd/k8/stage1.c endif endif endif @@ -130,11 +131,13 @@ PARSEELF = -e endif
-STAGE0_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE0_LIB_OBJ)) \ - $(patsubst %,$(obj)/arch/x86/%,$(STAGE0_ARCH_X86_OBJ)) \ - $(patsubst %,$(obj)/arch/x86/%,$(STAGE0_CAR_OBJ)) \ - $(STAGE0_MAINBOARD_OBJ) $(STAGE0_CHIPSET_OBJ) +STAGE0_SRC := $(patsubst %,$(src)/lib/%,$(STAGE0_LIB_SRC)) \ + $(patsubst %,$(src)/arch/x86/%,$(STAGE0_ARCH_X86_SRC)) \ + $(STAGE0_MAINBOARD_SRC) $(STAGE0_CHIPSET_SRC)
+STAGE0_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE0_SRC)) \ + $(patsubst %,$(obj)/arch/x86/%,$(STAGE0_CAR_OBJ)) + $(obj)/stage0.o $(obj)/stage0.init $(obj)/stage0-prefixed.o: $(STAGE0_OBJ) $(Q)# We need to be careful. If stage0.o gets bigger than $(Q)# 0x4000 - 0x100, we will end up with a 4 gig file. @@ -182,7 +185,7 @@ STAGE2_ARCH_X86_SRC += pirq_routing.c endif
-STAGE2_DYNAMIC_OBJ = statictree.o +STAGE2_DYNAMIC_SRC = $(obj)/mainboard/$(MAINBOARDDIR)/statictree.c
STAGE2_SRC := $(patsubst %,$(src)/lib/%,$(STAGE2_LIB_SRC)) \ $(patsubst %,$(src)/arch/x86/%,$(STAGE2_ARCH_X86_SRC)) \ @@ -195,7 +198,7 @@
# This one is special because the static tree object ends up in the mainboard # dir of the object tree. -STAGE2_OBJ += $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ)) +STAGE2_OBJ += $(patsubst $(obj)/%.c,$(obj)/%.o,$(STAGE2_DYNAMIC_SRC))
ifeq ($(CONFIG_PCI_OPTION_ROM_RUN),y) ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y)
Modified: coreboot-v3/lib/Makefile =================================================================== --- coreboot-v3/lib/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/lib/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -21,10 +21,10 @@
DECOMPRESSORS := ifeq ($(CONFIG_COMPRESSION_LZMA),y) -DECOMPRESSORS += lzma.o +DECOMPRESSORS += lzma.c endif ifeq ($(CONFIG_COMPRESSION_NRV2B),y) -DECOMPRESSORS += nrv2b.o +DECOMPRESSORS += nrv2b.c endif
#
Modified: coreboot-v3/mainboard/adl/msm800sev/Makefile =================================================================== --- coreboot-v3/mainboard/adl/msm800sev/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/mainboard/adl/msm800sev/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -19,7 +19,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o +STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \
Modified: coreboot-v3/mainboard/amd/db800/Makefile =================================================================== --- coreboot-v3/mainboard/amd/db800/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/mainboard/amd/db800/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -19,7 +19,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o +STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \
Modified: coreboot-v3/mainboard/amd/norwich/Makefile =================================================================== --- coreboot-v3/mainboard/amd/norwich/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/mainboard/amd/norwich/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -19,7 +19,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o +STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \
Modified: coreboot-v3/mainboard/amd/serengeti/Makefile =================================================================== --- coreboot-v3/mainboard/amd/serengeti/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/mainboard/amd/serengeti/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -19,14 +19,14 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o \ - $(obj)/mainboard/$(MAINBOARDDIR)/option_table.o \ - $(obj)/southbridge/amd/amd8111/stage1_smbus.o \ - $(obj)/southbridge/amd/amd8111/stage1_ctrl.o \ - $(obj)/northbridge/amd/k8/coherent_ht.o \ - $(obj)/northbridge/amd/k8/incoherent_ht.o \ - $(obj)/northbridge/amd/k8/libstage1.o \ - $(obj)/lib/clog2.o +STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ + $(src)/mainboard/$(MAINBOARDDIR)/option_table.c \ + $(src)/southbridge/amd/amd8111/stage1_smbus.c \ + $(src)/southbridge/amd/amd8111/stage1_ctrl.c \ + $(src)/northbridge/amd/k8/coherent_ht.c \ + $(src)/northbridge/amd/k8/incoherent_ht.c \ + $(src)/northbridge/amd/k8/libstage1.c \ + $(src)/lib/clog2.c
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/k8/raminit.c \
Modified: coreboot-v3/mainboard/artecgroup/dbe61/Makefile =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/mainboard/artecgroup/dbe61/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -19,7 +19,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o +STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \
Modified: coreboot-v3/mainboard/artecgroup/dbe62/Makefile =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/mainboard/artecgroup/dbe62/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -19,7 +19,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o +STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \
Modified: coreboot-v3/mainboard/emulation/qemu-x86/Makefile =================================================================== --- coreboot-v3/mainboard/emulation/qemu-x86/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/mainboard/emulation/qemu-x86/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -19,7 +19,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o +STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
# # This is going to be the init RAM code.
Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -19,12 +19,12 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o \ - $(obj)/mainboard/$(MAINBOARDDIR)/option_table.o \ - $(obj)/southbridge/nvidia/mcp55/stage1_smbus.o \ - $(obj)/northbridge/amd/k8/coherent_ht.o \ - $(obj)/northbridge/amd/k8/incoherent_ht.o \ - $(obj)/lib/clog2.o +STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ + $(src)/mainboard/$(MAINBOARDDIR)/option_table.c \ + $(src)/southbridge/nvidia/mcp55/stage1_smbus.c \ + $(src)/northbridge/amd/k8/coherent_ht.c \ + $(src)/northbridge/amd/k8/incoherent_ht.c \ + $(src)/lib/clog2.c
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/k8/raminit.c \
Modified: coreboot-v3/mainboard/pcengines/alix1c/Makefile =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/mainboard/pcengines/alix1c/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -19,7 +19,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o +STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \
Modified: coreboot-v3/mainboard/pcengines/alix2c3/Makefile =================================================================== --- coreboot-v3/mainboard/pcengines/alix2c3/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/mainboard/pcengines/alix2c3/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -19,7 +19,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o +STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \
Modified: coreboot-v3/southbridge/amd/amd8111/Makefile =================================================================== --- coreboot-v3/southbridge/amd/amd8111/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/southbridge/amd/amd8111/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -34,7 +34,7 @@ $(src)/southbridge/amd/amd8111/usb.c \ $(src)/southbridge/amd/amd8111/usb2.c -STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/amd8111/stage1.o +STAGE0_CHIPSET_SRC += $(src)/southbridge/amd/amd8111/stage1.c
endif
Modified: coreboot-v3/southbridge/amd/cs5536/Makefile =================================================================== --- coreboot-v3/southbridge/amd/cs5536/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/southbridge/amd/cs5536/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -27,6 +27,6 @@ STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/irq_tables.c endif
-STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o +STAGE0_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/stage1.c
endif
Modified: coreboot-v3/southbridge/nvidia/mcp55/Makefile =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/southbridge/nvidia/mcp55/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -36,7 +36,7 @@ $(src)/southbridge/nvidia/mcp55/usb.c \ $(src)/southbridge/nvidia/mcp55/usb2.c -STAGE0_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/stage1.o +STAGE0_CHIPSET_SRC += $(src)/southbridge/nvidia/mcp55/stage1.c
endif
Modified: coreboot-v3/superio/fintek/f71805f/Makefile =================================================================== --- coreboot-v3/superio/fintek/f71805f/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/superio/fintek/f71805f/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -20,8 +20,8 @@
ifeq ($(CONFIG_SUPERIO_FINTEK_F71805F),y)
-STAGE0_CHIPSET_OBJ += $(obj)/superio/fintek/f71805f/stage1.o -STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o +STAGE0_CHIPSET_SRC += $(src)/superio/fintek/f71805f/stage1.c +STAGE0_CHIPSET_SRC += $(src)/device/pnp_raw.c
# Always add to variables, as there could be more than one Super I/O. STAGE2_CHIPSET_SRC += $(src)/superio/fintek/f71805f/superio.c
Modified: coreboot-v3/superio/ite/it8716f/Makefile =================================================================== --- coreboot-v3/superio/ite/it8716f/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/superio/ite/it8716f/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -20,8 +20,8 @@
ifeq ($(CONFIG_SUPERIO_ITE_IT8716F),y)
-STAGE0_CHIPSET_OBJ += $(obj)/superio/ite/it8716f/stage1.o -STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o +STAGE0_CHIPSET_SRC += $(src)/superio/ite/it8716f/stage1.c +STAGE0_CHIPSET_SRC += $(src)/device/pnp_raw.c
# Always add to variables, as there could be more than one Super I/O. STAGE2_CHIPSET_SRC += $(src)/superio/ite/it8716f/superio.c
Modified: coreboot-v3/superio/winbond/w83627hf/Makefile =================================================================== --- coreboot-v3/superio/winbond/w83627hf/Makefile 2008-08-17 22:18:09 UTC (rev 781) +++ coreboot-v3/superio/winbond/w83627hf/Makefile 2008-08-18 11:15:43 UTC (rev 782) @@ -21,8 +21,8 @@
ifeq ($(CONFIG_SUPERIO_WINBOND_W83627HF),y)
-STAGE0_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/stage1.o -STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o +STAGE0_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/stage1.c +STAGE0_CHIPSET_SRC += $(src)/device/pnp_raw.c
# Always add to variables, as there could be more than one Super I/O. STAGE2_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/superio.c
-
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