Hi all,
I'm lost how to build a new BIOS for a Geode GX / CS5535 board.
http://www.coreboot.org/AMD_Geode_Porting_Guide is focused on the Geode LX and a db800 reference board.
I've found the CS5535 sources at http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/sout... but don't know how to use them.
The CPU is a Geode GX 500 http://tracker.coreboot.org/trac/coreboot/browser/trunk/coreboot-v2/src/cpu/...
The board is an AMD Personal Internet Communicator (PIC, now DecTOP): http://50x15.amd.com/en-us/sol_tech_dectop.aspx http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330...
Unfortunately I do not know any access to the board's schematics. AMD has cancelled this project. I'm afraid that its docu is lost.
coreboot v3 does not include the GX/CS5535 yet. I don't know whether I should learn how to use v2 or whether v3 will include those soon.
Thanks for any help, Martin
On Thu, Feb 28, 2008 at 11:40:33PM +0100, Martin Trautmann wrote:
coreboot v3 does not include the GX/CS5535 yet. I don't know whether I should learn how to use v2 or whether v3 will include those soon.
GX and 5535 are supported in v2. I believe the next hardware endeavour for v3 will be K8, so v2 is likely your best bet.
//Peter
Peter Stuge wrote:
GX and 5535 are supported in v2. I believe the next hardware endeavour for v3 will be K8, so v2 is likely your best bet.
Thanks, I'll give v2 a try.
Here's the lspci output:
$ lspci 00:01.0 Host bridge: National Semiconductor Corporation Geode GX2 Host Bridge (rev 21) 00:01.1 VGA compatible controller: National Semiconductor Corporation Geode GX2 Graphics Processor 00:0d.0 Communication controller: Agere Systems LT WinModem (rev 02) 00:0f.0 ISA bridge: National Semiconductor Corporation CS5535 ISA bridge (rev 13) 00:0f.2 IDE interface: National Semiconductor Corporation CS5535 IDE 00:0f.3 Multimedia audio controller: National Semiconductor Corporation CS5535 Audio 00:0f.4 USB Controller: National Semiconductor Corporation CS5535 USB (rev 06) 00:0f.5 USB Controller: National Semiconductor Corporation CS5535 USB (rev 06)
Martin Trautmann wrote:
Here's the lspci output:
flashrom identifies the SST49LF002A/B (256 KB)
I don't know what the Super I/O chip might be.
On Fri, Feb 29, 2008 at 06:51:07AM +0100, Martin Trautmann wrote:
Martin Trautmann wrote:
Here's the lspci output:
flashrom identifies the SST49LF002A/B (256 KB)
I don't know what the Super I/O chip might be.
Please post the result of 'superiotool -dV'. It's also possible that your board doesn't have any superio. If you can post a photo of the board somewhere that may also help.
Uwe.
Uwe Hermann wrote:
I don't know what the Super I/O chip might be.
Please post the result of 'superiotool -dV'. It's also possible that your board doesn't have any superio.
I think so: superiotool r3117 [...] No Super I/O found
If you can post a photo of the board somewhere that may also help.
The board and all ICs are described on http://www.nottoxic.com/wapcc/dectop/wiki/doku.php?id=hardware:dectop:techni... - it's a German merged order of 100 devices from Data Evolution
Here's the board itself: http://www.nottoxic.com/wapcc/dectop/wiki/lib/exe/fetch.php?cache=cache&media=hardware:dectop:dectoplb.jpg
An English description can be found on http://dectop.nfshost.com/wiki/index.php/DecTOP_hardware
Thanks, Martin
On Fri, Feb 29, 2008 at 04:45:38PM +0100, Martin Trautmann wrote:
Please post the result of 'superiotool -dV'. It's also possible that your board doesn't have any superio.
I think so: superiotool r3117 [...] No Super I/O found
Ehm, you stripped the really important parts ;) Please repost the _full_ superiotool -dV. But yeah, it's likely that there isn't any superio.
If you can post a photo of the board somewhere that may also help.
The board and all ICs are described on http://www.nottoxic.com/wapcc/dectop/wiki/doku.php?id=hardware:dectop:techni...
- it's a German merged order of 100 devices from Data Evolution
Here's the board itself: http://www.nottoxic.com/wapcc/dectop/wiki/lib/exe/fetch.php?cache=cache&media=hardware:dectop:dectoplb.jpg
The BIOS chip is soldered. Make sure you do _not_ try to flash any code on it unless you are able to desolder the chip in case something goes wrong!
An English description can be found on http://dectop.nfshost.com/wiki/index.php/DecTOP_hardware
Uwe.
Uwe Hermann wrote:
On Fri, Feb 29, 2008 at 04:45:38PM +0100, Martin Trautmann wrote:
Please post the result of 'superiotool -dV'. It's also possible that your board doesn't have any superio.
I think so: superiotool r3117 [...] No Super I/O found
Ehm, you stripped the really important parts ;) Please repost the _full_ superiotool -dV. But yeah, it's likely that there isn't any superio.
Here we go:
superiotool r3117 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff No Super I/O found
On 29.02.2008 17:37, Martin Trautmann wrote:
Uwe Hermann wrote:
On Fri, Feb 29, 2008 at 04:45:38PM +0100, Martin Trautmann wrote:
Please post the result of 'superiotool -dV'. It's also possible that your board doesn't have any superio.
I think so: superiotool r3117 [...] No Super I/O found
Ehm, you stripped the really important parts ;) Please repost the _full_ superiotool -dV. But yeah, it's likely that there isn't any superio.
Here we go:
superiotool r3117 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff [...]
superiotool is missing detection of Geode on-chip superio functionality.
Regards, Carl-Daniel
On Fri, Feb 29, 2008 at 05:11:31PM +0100, Uwe Hermann wrote:
Here's the board itself: http://www.nottoxic.com/wapcc/dectop/wiki/lib/exe/fetch.php?cache=cache&...
The BIOS chip is soldered.
It looks like J11 may also have the LPC bus signals. If the boot flash selector ball is also on J11 you could use Artec's dongle or just another LPC flash chip to work on coreboot rather than having to desolder the existing chip.
//Peter
Peter Stuge wrote:
On Fri, Feb 29, 2008 at 05:11:31PM +0100, Uwe Hermann wrote:
Here's the board itself: http://www.nottoxic.com/wapcc/dectop/wiki/lib/exe/fetch.php?cache=cache&...
The BIOS chip is soldered.
It looks like J11 may also have the LPC bus signals.
Could be.
I assumed LVDS on http://www.nottoxic.com/wapcc/dectop/wiki/doku.php?id=hardware:dectop:erweit... - I'll have to check e.g. the voltage levels on pins 8/18 (5 or 3.3V) and 19/20 (12 V). Is there a typical default pinout for LPC?
http://www.artecgroup.com/downloads/task,doc_download/gid,5/Itemid,33/ could use anything.
I've seen other applications which used 20 pin connectors for GPIO purposes
If the boot flash selector ball is also on J11 you could use Artec's dongle or just another LPC flash chip to work on coreboot rather than having to desolder the existing chip.
I know that the BIOS can be programmed easily onboard since there's a Windows software around to reprogram it.
Is there any kind of de-assembler within coreboot that would help to find out what the current BIOS versions do?
Thanks, Martin
On 29/02/08 01:43 +0100, Peter Stuge wrote:
On Thu, Feb 28, 2008 at 11:40:33PM +0100, Martin Trautmann wrote:
coreboot v3 does not include the GX/CS5535 yet. I don't know whether I should learn how to use v2 or whether v3 will include those soon.
GX and 5535 are supported in v2. I believe the next hardware endeavour for v3 will be K8, so v2 is likely your best bet.
GX/5535 in v3 would be a fairly straightforward port of the already existing LX support, and would be a great way for somebody who wants to learn about the deep down internals of the Geode architecture.
Jordan
Jordan Crouse wrote:
GX/5535 in v3 would be a fairly straightforward port of the already existing LX support, and would be a great way for somebody who wants to learn about the deep down internals of the Geode architecture.
That much encouragement ;-)
I'll have a look - but as an absolute beginner on coreboot bios stuff I doubt that this would work out very well.
Thanks, Martin
Jordan Crouse wrote:
GX/5535 in v3 would be a fairly straightforward port of the already existing LX support, and would be a great way for somebody who wants to learn about the deep down internals of the Geode architecture.
Is there any HOWTO migrate? I know that there are about 1000 lines of different code between CS5535 and CS5536 in v2, while CS5536 in v2 is very different to the same in v3.
I did try to find out about the differnces in v2 and repeat the same process in v3 from CS5536 to CS5535 - but I feel I miss the basic understanding and do some simple try'n'error only.
Thanks, Martin
-
Carl-Daniel Hailfinger -
Jordan Crouse -
Martin Trautmann -
Peter Stuge -
Uwe Hermann