PIC, APIC, XAPIC and XIOAPIC

[Feng, Libo]

Hi, all,

I am a little confused by PIC, APIC, XAPIC and XIOAPIC.

In LB stage, only PIC mode is applied, isn't it? However, I remember some people of LB community told me there was no ISR except the debug ISR during LB. So does this mean it totally unnecessary to setup PIC via C00h/C001h IO port in LB?

APIC is setup only after OS runs and gets the interrupt routing from MPTable or ACPI table, is it correct? Then, what difference between APIC and XAPIC? Some documents say APIC has MMIO space registers at FEC00000h while XAPIC has PCI configuration space registers. But some documents seems to refer the same controller by APIC and XAPIC.

And XAPIC and XIOAPIC are the same things, aren’t they?

Please help me out, I am completely confused by these terms.

Best Regards

丰立波 Feng Libo @ AMD  Ext: 20906
Mobile Phone: [phone]
Office Phone: [phone]

[ron minnich]

On Tue, Mar 4, 2008 at 2:08 AM, Feng, Libo  wrote:
> In LB stage, only PIC mode is applied, isn't it? However, I remember some
> people of LB community told me there was no ISR except the debug ISR during
> LB. So does this mean it totally unnecessary to setup PIC via C00h/C001h IO
> port in LB?

PIC is set up in many mainboards so it is ready for the kernel. This
is because so many $PIR tables are wrong.

PIC is not needed for ISR, but coreboot only does ISR for the case of
running PCI (or VGA) ROMs anyway.
> APIC is setup only after OS runs and gets the interrupt routing from MPTable
> or ACPI table, is it correct? Then, what difference between APIC and XAPIC?
> Some documents say APIC has MMIO space registers at FEC00000h while XAPIC
> has PCI configuration space registers. But some documents seems to refer the
> same controller by APIC and XAPIC.

APIC is set up by kernel.

ron

[Segher Boessenkool]

> In LB stage, only PIC mode is applied, isn't it? However, I remember 
> some people of LB community told me there was no ISR except the debug 
> ISR during LB. So does this mean it totally unnecessary to setup PIC 
> via C00h/C001h IO port in LB?

You need to set up the legacy PIC really early, since it doesn't 
initialise
itself to any sane settings at bootup.

Segher

[Feng, Libo]

Hi, all,

I check the FILO code, all devices work under polling mode. So I think at the very beginning of initialization, OS probably needs the legacy PIC enabled before APIC mode enabled.

Best Regards

??? Feng Libo @ AMD  Ext: 20906
Mobile Phone: [phone]
Office Phone: [phone]

-----Original Message-----
From: Segher Boessenkool [mailto:[e-mail]] 
Sent: Wednesday, March 05, 2008 4:10 AM
To: Feng, Libo
Cc: [e-mail]
Subject: Re: [coreboot] PIC, APIC, XAPIC and XIOAPIC
> In LB stage, only PIC mode is applied, isn't it? However, I remember 
> some people of LB community told me there was no ISR except the debug 
> ISR during LB. So does this mean it totally unnecessary to setup PIC 
> via C00h/C001h IO port in LB?

You need to set up the legacy PIC really early, since it doesn't initialise itself to any sane settings at bootup.

Segher

[Rudolf Marek]

Hello,

You need to put at least SB IOAPICs in virtualwire mode. Thats what BIOS should 
do. CHeck the Multiprocessor Specs 1.4 for details. (or VIA 8237 code in 
southbridge/)

http://www.intel.com/design/intarch/MANUALS/242016.htm

Rudolf

[Feng, Libo]

Yes. I think that after power on, IOAPIC works on PIC mode or virtual wire mode by default. But no device use interrupts in both coreboot and FILO, keyboard, vga, serial port all polling. I check the mptable.c, some people set the IOAPIC in PIC mode via c00h/c01h, now that no device uses it, why they set it? Maybe at the very beginning of OS, PIC mode is applied before IOAPIC is enabled. My understanding is correct or not? Thank you.

Best Regards

??? Feng Libo @ AMD  Ext: 20906
Mobile Phone: [phone]
Office Phone: [phone]

-----Original Message-----
From: Rudolf Marek [mailto:[e-mail]] 
Sent: Wednesday, March 05, 2008 4:11 PM
To: Feng, Libo
Cc: [e-mail]
Subject: Re: [coreboot] PIC, APIC, XAPIC and XIOAPIC

Hello,

You need to put at least SB IOAPICs in virtualwire mode. Thats what BIOS should do. CHeck the Multiprocessor Specs 1.4 for details. (or VIA 8237 code in
southbridge/)

http://www.intel.com/design/intarch/MANUALS/242016.htm

Rudolf

[Rudolf Marek]

Feng, Libo wrote:
> Yes. I think that after power on, IOAPIC works on PIC mode or virtual wire
> mode by default. But no device use interrupts in both coreboot and FILO,
> keyboard, vga, serial port all polling. I check the mptable.c, some people
> set the IOAPIC in PIC mode via c00h/c01h, now that no device uses it, why
> they set it? Maybe at the very beginning of OS, PIC mode is applied before
> IOAPIC is enabled. My understanding is correct or not? Thank you.

Yes its true, there is short period of time where PIC is used. So it is later 
switched to APIC.

Thanks,
Rudolf