Denis Carikli (GNUtoo@no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/457
-gerrit
commit 1eb55d026f9d364eb8f3d7ededc4dc7f98deafef Author: Denis 'GNUtoo' Carikli GNUtoo@no-log.org Date: Sun Nov 27 15:58:38 2011 +0100
Add ASUS M4A785T-M mainboard support
This mainboard is very similar to the M4A785-M, but it has DDR3 instead of DDR2.
That's why most of the code was copied or included from the m4a785-m directory
Notable changes between the two mainboards include: * the selection of the last microcode (mc_patch_010000b6.h) which made it pass the CPU init. * the selection of DDR3 which made it pass the ram init
Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732 Signed-off-by: Denis 'GNUtoo' Carikli GNUtoo@no-log.org --- src/mainboard/asus/Kconfig | 3 + src/mainboard/asus/m4a785-m/mainboard.c | 4 + src/mainboard/asus/m4a785t-m/Kconfig | 86 ++ src/mainboard/asus/m4a785t-m/acpi/cpstate.asl | 75 + src/mainboard/asus/m4a785t-m/acpi/ide.asl | 244 ++++ src/mainboard/asus/m4a785t-m/acpi/routing.asl | 300 ++++ src/mainboard/asus/m4a785t-m/acpi/sata.asl | 149 ++ src/mainboard/asus/m4a785t-m/acpi/usb.asl | 161 +++ src/mainboard/asus/m4a785t-m/acpi_tables.c | 21 + src/mainboard/asus/m4a785t-m/chip.h | 23 + src/mainboard/asus/m4a785t-m/cmos.layout | 98 ++ src/mainboard/asus/m4a785t-m/devicetree.cb | 106 ++ src/mainboard/asus/m4a785t-m/dsdt.asl | 1850 +++++++++++++++++++++++++ src/mainboard/asus/m4a785t-m/get_bus_conf.c | 21 + src/mainboard/asus/m4a785t-m/irq_tables.c | 21 + src/mainboard/asus/m4a785t-m/mainboard.c | 21 + src/mainboard/asus/m4a785t-m/mptable.c | 21 + src/mainboard/asus/m4a785t-m/romstage.c | 21 + 18 files changed, 3225 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig index 77b7997..bdc1709 100644 --- a/src/mainboard/asus/Kconfig +++ b/src/mainboard/asus/Kconfig @@ -35,6 +35,8 @@ config BOARD_ASUS_M2V_MX_SE bool "M2V-MX SE" config BOARD_ASUS_M4A785M bool "M4A785-M" +config BOARD_ASUS_M4A785TM + bool "M4A785T-M" config BOARD_ASUS_M4A78_EM bool "M4A78-EM" config BOARD_ASUS_M5A88_V @@ -65,6 +67,7 @@ source "src/mainboard/asus/m2n-e/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" source "src/mainboard/asus/m4a785-m/Kconfig" +source "src/mainboard/asus/m4a785t-m/Kconfig" source "src/mainboard/asus/m4a78-em/Kconfig" source "src/mainboard/asus/m5a88-v/Kconfig" source "src/mainboard/asus/mew-am/Kconfig" diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index 8a96476..d152f71 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -242,6 +242,10 @@ static void m4a785m_enable(device_t dev) }
struct chip_operations mainboard_ops = { +#ifdef CONFIG_BOARD_ASUS_M4A785TM + CHIP_NAME("ASUS M4A785T-M Mainboard") +#else CHIP_NAME("ASUS M4A785-M Mainboard") +#endif .enable_dev = m4a785m_enable, }; diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig new file mode 100644 index 0000000..e3893b2 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -0,0 +1,86 @@ +if BOARD_ASUS_M4A785TM + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_AM3 + select DIMM_DDR3 + select DIMM_REGISTERED + select NORTHBRIDGE_AMD_AMDFAM10 + select SOUTHBRIDGE_AMD_RS780 + select SOUTHBRIDGE_AMD_SB700 + select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT + select SUPERIO_ITE_IT8712F + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO + select ENABLE_APIC_EXT_ID + select GFXUMA + select QRANK_DIMM_SUPPORT + +config MAINBOARD_DIR + string + default asus/m4a785t-m + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "M4A785T-M" + +config MAX_CPUS + int + default 8 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config MEM_TRAIN_SEQ + int + default 2 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x1 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +config IRQ_SLOT_COUNT + int + default 19 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_010000c4.h" + +config RAMTOP + hex + default 0x2000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config RAMBASE + hex + default 0x200000 + +endif diff --git a/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl new file mode 100644 index 0000000..6a1b002 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/cpstate.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package () + { + 0x00000AF0, + 0x0000BF81, + 0x00000002, + 0x00000002, + 0x00000000, + 0x00000000 + }, + + Package () + { + 0x00000578, + 0x000076F2, + 0x00000002, + 0x00000002, + 0x00000001, + 0x00000001 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/asus/m4a785t-m/acpi/ide.asl b/src/mainboard/asus/m4a785t-m/acpi/ide.asl new file mode 100644 index 0000000..6ea2b09 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/asus/m4a785t-m/acpi/routing.asl b/src/mainboard/asus/m4a785t-m/acpi/routing.asl new file mode 100644 index 0000000..ad51815 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/routing.asl @@ -0,0 +1,300 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, INTB, 0 }, */ + /* Package(){0x0005FFFF, 1, INTC, 0 }, */ + /* Package(){0x0005FFFF, 2, INTD, 0 }, */ + /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 1, INTA, 0 }, + + /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ + Package(){0x0012FFFF, 0, INTA, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + Package(){0x0013FFFF, 0, INTA, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTA, 0 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + /* Package(){0x0001FFFF, 0, 0, 18 }, */ + /* package(){0x0001FFFF, 1, 0, 19 }, */ + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + /* Package(){0x0004FFFF, 1, 0, 17 }, */ + /* Package(){0x0004FFFF, 2, 0, 18 }, */ + /* Package(){0x0004FFFF, 3, 0, 19 }, */ + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, 0, 17 }, */ + /* Package(){0x0005FFFF, 1, 0, 18 }, */ + /* Package(){0x0005FFFF, 2, 0, 19 }, */ + /* Package(){0x0005FFFF, 3, 0, 16 }, */ + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Package(){0x0006FFFF, 0, 0, 18 }, */ + /* Package(){0x0006FFFF, 1, 0, 19 }, */ + /* Package(){0x0006FFFF, 2, 0, 16 }, */ + /* Package(){0x0006FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Package(){0x0007FFFF, 0, 0, 19 }, */ + /* Package(){0x0007FFFF, 1, 0, 16 }, */ + /* Package(){0x0007FFFF, 2, 0, 17 }, */ + /* Package(){0x0007FFFF, 3, 0, 18 }, */ + + /* Bus 0, Dev 9 - PCIe Bridge for network card */ + Package(){0x0009FFFF, 0, 0, 17 }, + /* Package(){0x0009FFFF, 1, 0, 16 }, */ + /* Package(){0x0009FFFF, 2, 0, 17 }, */ + /* Package(){0x0009FFFF, 3, 0, 18 }, */ + /* Bus 0, Dev A - PCIe Bridge for network card */ + Package(){0x000AFFFF, 0, 0, 18 }, + /* Package(){0x000AFFFF, 1, 0, 16 }, */ + /* Package(){0x000AFFFF, 2, 0, 17 }, */ + /* Package(){0x000AFFFF, 3, 0, 18 }, */ + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, 0, 22 }, + + /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ + Package(){0x0012FFFF, 0, 0, 16 }, + Package(){0x0012FFFF, 1, 0, 17 }, + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 19 }, + Package(){0x0014FFFF, 0, 0, 16 }, + /* Package(){0x00130004, 2, 0, 18 }, */ + /* Package(){0x00130005, 3, 0, 19 }, */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + Name(PS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + Name(PSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + Package(){0x0006FFFF, 0, 0, 0x15 }, + Package(){0x0006FFFF, 1, 0, 0x16 }, + Package(){0x0006FFFF, 2, 0, 0x17 }, + Package(){0x0006FFFF, 3, 0, 0x14 }, + Package(){0x0007FFFF, 0, 0, 0x16 }, + Package(){0x0007FFFF, 1, 0, 0x17 }, + Package(){0x0007FFFF, 2, 0, 0x14 }, + Package(){0x0007FFFF, 3, 0, 0x15 }, + }) +} diff --git a/src/mainboard/asus/m4a785t-m/acpi/sata.asl b/src/mainboard/asus/m4a785t-m/acpi/sata.asl new file mode 100644 index 0000000..b5e6fc5 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/sata.asl @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + _GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (_SB.P0PR) { + if (LGreater(_SB.P0IS,0)) { + sleep(32) + } + Notify(_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, _SB.P0PR) + } + + if (_SB.P1PR) { + if (LGreater(_SB.P1IS,0)) { + sleep(32) + } + Notify(_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, _SB.P1PR) + } + + if (_SB.P2PR) { + if (LGreater(_SB.P2IS,0)) { + sleep(32) + } + Notify(_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, _SB.P2PR) + } + + if (_SB.P3PR) { + if (LGreater(_SB.P3IS,0)) { + sleep(32) + } + Notify(_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, _SB.P3PR) + } + } +} diff --git a/src/mainboard/asus/m4a785t-m/acpi/usb.asl b/src/mainboard/asus/m4a785t-m/acpi/usb.asl new file mode 100644 index 0000000..203e0ad --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi/usb.asl @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, _SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, _SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, _SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, _SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, _SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, _SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, _SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, _SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, _SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/asus/m4a785t-m/acpi_tables.c b/src/mainboard/asus/m4a785t-m/acpi_tables.c new file mode 100644 index 0000000..a7ffc02 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli GNUtoo@no-log.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/acpi_tables.c" diff --git a/src/mainboard/asus/m4a785t-m/chip.h b/src/mainboard/asus/m4a785t-m/chip.h new file mode 100644 index 0000000..a98b97e --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/asus/m4a785t-m/cmos.layout b/src/mainboard/asus/m4a785t-m/cmos.layout new file mode 100644 index 0000000..53fdef5 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/cmos.layout @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb new file mode 100644 index 0000000..e8764b1 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/devicetree.cb @@ -0,0 +1,106 @@ +chip northbridge/amd/amdfam10/root_complex + device lapic_cluster 0 on + chip cpu/amd/socket_AM3 #L1 and DDR2 + device lapic 0 on end + end + end + device pci_domain 0 on + subsystemid 0x1043 0x83a2 inherit + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 off end # PCIE P2P bridge 0x960b + device pci 4.0 off end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 off end # + device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "2" + + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8712f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + end + device pnp 2e.9 off # GAME + end + device pnp 2e.a off end # CIR + end #superio + end #LPC + device pci 14.4 on end # PCI to PCI Bridge [1002:4384] + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end # chip northbridge + end #pci_domain +end # northbridge/amd/amdfam10/root_complex diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl new file mode 100644 index 0000000..34ddd3a --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -0,0 +1,1850 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "ASUS ", /* OEMID */ + "M4A785-M ", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* USB overcurrent mapping pins. */ + Name(UOM0, 0) + Name(UOM1, 2) + Name(UOM2, 0) + Name(UOM3, 7) + Name(UOM4, 2) + Name(UOM5, 2) + Name(UOM6, 6) + Name(UOM7, 2) + Name(UOM8, 6) + Name(UOM9, 6) + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* + * Processor Object + * + */ + Scope (_PR) { /* define processor scope */ + Processor( + CPU0, /* name space name */ + 0, /* Unique number for this processor */ + 0x808, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU1, /* name space name */ + 1, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU2, /* name space name */ + 2, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU3, /* name space name */ + 3, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PINA, 0x00000008, /* Index 0 */ + PINB, 0x00000008, /* Index 1 */ + PINC, 0x00000008, /* Index 2 */ + PIND, 0x00000008, /* Index 3 */ + AINT, 0x00000008, /* Index 4 */ + SINT, 0x00000008, /* Index 5 */ + , 0x00000008, /* Index 6 */ + AAUD, 0x00000008, /* Index 7 */ + AMOD, 0x00000008, /* Index 8 */ + PINE, 0x00000008, /* Index 9 */ + PINF, 0x00000008, /* Index A */ + PING, 0x00000008, /* Index B */ + PINH, 0x00000008, /* Index C */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x00), /* MiscControl */ + , 1, + T1EE, 1, + T2EE, 1, + Offset(0x01), /* MiscStatus */ + , 1, + T1E, 1, + T2E, 1, + Offset(0x04), /* SmiWakeUpEventEnable3 */ + , 7, + SSEN, 1, + Offset(0x07), /* SmiWakeUpEventStatus3 */ + , 7, + CSSM, 1, + Offset(0x10), /* AcpiEnable */ + , 6, + PWDE, 1, + Offset(0x1C), /* ProgramIoEnable */ + , 3, + MKME, 1, + IO3E, 1, + IO2E, 1, + IO1E, 1, + IO0E, 1, + Offset(0x1D), /* IOMonitorStatus */ + , 3, + MKMS, 1, + IO3S, 1, + IO2S, 1, + IO1S, 1, + IO0S,1, + Offset(0x20), /* AcpiPmEvtBlk */ + APEB, 16, + Offset(0x36), /* GEvtLevelConfig */ + , 6, + ELC6, 1, + ELC7, 1, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x3B), /* PMEStatus1 */ + GP0S, 1, + GM4S, 1, + GM5S, 1, + APS, 1, + GM6S, 1, + GM7S, 1, + GP2S, 1, + STSS, 1, + Offset(0x55), /* SoftPciRst */ + SPRE, 1, + , 1, + , 1, + PNAT, 1, + PWMK, 1, + PWNS, 1, + + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ + + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x68), /* MiscEnable68 */ + , 3, + TMTE, 1, + , 1, + Offset(0x92), /* GEVENTIN */ + , 7, + E7IS, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xA8), /* PIO7654Enable */ + IO4E, 1, + IO5E, 1, + IO6E, 1, + IO7E, 1, + Offset(0xA9), /* PIO7654Status */ + IO4S, 1, + IO5S, 1, + IO6S, 1, + IO7S, 1, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1EB, SystemIO, APEB, 0x04) + Field(P1EB, ByteAcc, NoLock, Preserve) { + TMST, 1, + , 3, + BMST, 1, + GBST, 1, + Offset(0x01), + PBST, 1, + , 1, + RTST, 1, + , 3, + PWST, 1, + SPWS, 1, + Offset(0x02), + TMEN, 1, + , 4, + GBEN, 1, + Offset(0x03), + PBEN, 1, + , 1, + RTEN, 1, + , 3, + PWDA, 1, + } + + Scope(_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + + #include "acpi/routing.asl" + + Scope(_SB) { + + Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + _SB.CIRQ() + } + Store(Arg0, PMOD) + } + Method(CIRQ, 0x00, NotSerialized){ + Store(0, PINA) + Store(0, PINB) + Store(0, PINC) + Store(0, PIND) + Store(0, PINE) + Store(0, PINF) + Store(0, PING) + Store(0, PINH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PINA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\_SB\LNKA\_DIS\n") */ + Store(0, PINA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\_SB\LNKA\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\_SB\LNKA\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\_SB\LNKA\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PINB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\_SB\LNKB\_DIS\n") */ + Store(0, PINB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\_SB\LNKB\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\_SB\LNKB\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\_SB\LNKB\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PINC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\_SB\LNKC\_DIS\n") */ + Store(0, PINC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\_SB\LNKC\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\_SB\LNKC\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\_SB\LNKC\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIND) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\_SB\LNKD\_DIS\n") */ + Store(0, PIND) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\_SB\LNKD\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\_SB\LNKD\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIND, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\_SB\LNKD\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIND) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PINE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\_SB\LNKE\_DIS\n") */ + Store(0, PINE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\_SB\LNKE\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\_SB\LNKE\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\_SB\LNKE\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PINF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\_SB\LNKF\_DIS\n") */ + Store(0, PINF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\_SB\LNKF\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\_SB\LNKF\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\_SB\LNKF\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PING) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\_SB\LNKG\_DIS\n") */ + Store(0, PING) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\_SB\LNKG\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\_SB\LNKG\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PING, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\_SB\LNKG\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PING) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PINH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\_SB\LNKH\_DIS\n") */ + Store(0, PINH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\_SB\LNKH\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\_SB\LNKH\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\_SB\LNKH\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * _PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(_PTS, 1) { + /* DBGO("\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(_SB.SBRI, 0x13)) { + * Store(0,_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + _SB.PCI0.SIOS (Arg0) + } /* End Method(_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * _GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(_GTS, 1) { + * DBGO("\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * _BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(_BFS, 1) { + /* DBGO("\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * _WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(_WAK, 1) { + /* DBGO("\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + _SB.PCI0.SIOW (Arg0) + Return(WKST) + } /* End Method(_WAK) */ + + Scope(_GPE) { /* Start Scope GPE */ + /* General event 0 */ + /* Method(_L00) { + * DBGO("\_GPE\_L00\n") + * } + */ + + /* General event 1 */ + /* Method(_L01) { + * DBGO("\_GPE\_L00\n") + * } + */ + + /* General event 2 */ + /* Method(_L02) { + * DBGO("\_GPE\_L00\n") + * } + */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\_GPE\_L00\n") */ + Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + /* Method(_L04) { + * DBGO("\_GPE\_L00\n") + * } + */ + + /* General event 5 */ + /* Method(_L05) { + * DBGO("\_GPE\_L00\n") + * } + */ + + /* General event 6 - Used for GPM6, moved to USB.asl */ + /* Method(_L06) { + * DBGO("\_GPE\_L00\n") + * } + */ + + /* General event 7 - Used for GPM7, moved to USB.asl */ + /* Method(_L07) { + * DBGO("\_GPE\_L07\n") + * } + */ + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\_GPE\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\_GPE\_L09\n") */ + Notify (_TZ.TZ00, 0x80) + } + + /* Reserved */ + /* Method(_L0A) { + * DBGO("\_GPE\_L0A\n") + * } + */ + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\_GPE\_L0B\n") */ + Notify(_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + /* Method(_L0C) { + * DBGO("\_GPE\_L0C\n") + * } + */ + + /* OtherTherm PME# */ + /* Method(_L0D) { + * DBGO("\_GPE\_L0D\n") + * } + */ + + /* GPM9 SCI event - Moved to USB.asl */ + /* Method(_L0E) { + * DBGO("\_GPE\_L0E\n") + * } + */ + + /* PCIe HotPlug event */ + /* Method(_L0F) { + * DBGO("\_GPE\_L0F\n") + * } + */ + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\_GPE\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\_GPE\_L11\n") */ + } + + /* PCIe PME# event */ + /* Method(_L12) { + * DBGO("\_GPE\_L12\n") + * } + */ + + /* GPM0 SCI event - Moved to USB.asl */ + /* Method(_L13) { + * DBGO("\_GPE\_L13\n") + * } + */ + + /* GPM1 SCI event - Moved to USB.asl */ + /* Method(_L14) { + * DBGO("\_GPE\_L14\n") + * } + */ + + /* GPM2 SCI event - Moved to USB.asl */ + /* Method(_L15) { + * DBGO("\_GPE\_L15\n") + * } + */ + + /* GPM3 SCI event - Moved to USB.asl */ + /* Method(_L16) { + * DBGO("\_GPE\_L16\n") + * } + */ + + /* GPM8 SCI event - Moved to USB.asl */ + /* Method(_L17) { + * DBGO("\_GPE\_L17\n") + * } + */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\_GPE\_L18\n") */ + Notify(_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM4 SCI event - Moved to USB.asl */ + /* Method(_L19) { + * DBGO("\_GPE\_L19\n") + * } + */ + + /* GPM5 SCI event - Moved to USB.asl */ + /* Method(_L1A) { + * DBGO("\_GPE\_L1A\n") + * } + */ + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\_GPE\_L1B\n") */ + Notify(_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + /* Method(_L1C) { + * DBGO("\_GPE\_L1C\n") + * } + */ + + /* GPM7 SCI event - Reassigned to _L07 */ + /* Method(_L1D) { + * DBGO("\_GPE\_L1D\n") + * } + */ + + /* GPIO2 or GPIO66 SCI event */ + /* Method(_L1E) { + * DBGO("\_GPE\_L1E\n") + * } + */ + + /* SATA SCI event - Moved to sata.asl */ + /* Method(_L1F) { + * DBGO("\_GPE\_L1F\n") + * } + */ + + } /* End Scope GPE */ + + #include "acpi/usb.asl" + + /* South Bridge */ + Scope(_SB) { /* Start _SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the _SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\_SB\PCI0\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + + Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + Return (APR1) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* Dev3 is also an external GFX bridge, not used in Herring */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + /* GPP */ + Device(PBR9) { + Name(_ADR, 0x00090000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR9 */ + + Device(PBRa) { + Name(_ADR, 0x000A0000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ + } /* end _PRT */ + } /* end PBRa */ + + + /* PCI slot 1, 2, 3 */ + Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } + } + + /* Describe the Southbridge devices */ + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + Device(UOH1) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH1 */ + + Device(UOH2) { + Name(_ADR, 0x00130001) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH2 */ + + Device(UOH3) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH3 */ + + Device(UOH4) { + Name(_ADR, 0x00130003) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH4 */ + + Device(UOH5) { + Name(_ADR, 0x00130004) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00130005) + Name(_PRW, Package() {0x0B, 3}) + } /* end UEH1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method(_INI) { + If(LEqual(OSTP,3)){ /* If we are running Linux */ + Store(zero, NSEN) + Store(one, NSDO) + Store(one, NSDI) + } + } + } /* end AZHD */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\_SB\PCI0\LpcIsaBr\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + + Device(HPTM) { + Name(_HID,EISAID("PNP0103")) + Name(CRS,ResourceTemplate() { + Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ + }) + Method(_STA, 0) { + Return(0x0F) /* sata is visible */ + } + Method(_CRS, 0) { + CreateDwordField(CRS, ^HPT._BAS, HPBA) + Store(HPBA, HPBA) + Return(CRS) + } + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + } /* end LIBR */ + + Device(HPBR) { + Name(_ADR, 0x00140004) + } /* end HostPciBr */ + + Device(ACAD) { + Name(_ADR, 0x00140005) + } /* end Ac97audio */ + + Device(ACMD) { + Name(_ADR, 0x00140006) + } /* end Ac97modem */ + + /* ITE8718 Support */ + OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ + Field (IOID, ByteAcc, NoLock, Preserve) + { + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + } + + IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + LDN, 8, /* Logical Device Number */ + Offset (0x20), + CID1, 8, /* Chip ID Byte 1, 0x87 */ + CID2, 8, /* Chip ID Byte 2, 0x12 */ + Offset (0x30), + ACTR, 8, /* Function activate */ + Offset (0xF0), + APC0, 8, /* APC/PME Event Enable Register */ + APC1, 8, /* APC/PME Status Register */ + APC2, 8, /* APC/PME Control Register 1 */ + APC3, 8, /* Environment Controller Special Configuration Register */ + APC4, 8 /* APC/PME Control Register 2 */ + } + + /* Enter the 8718 MB PnP Mode */ + Method (EPNP) + { + Store(0x87, SIOI) + Store(0x01, SIOI) + Store(0x55, SIOI) + Store(0x55, SIOI) /* 8718 magic number */ + } + /* Exit the 8718 MB PnP Mode */ + Method (XPNP) + { + Store (0x02, SIOI) + Store (0x02, SIOD) + } + /* + * Keyboard PME is routed to SB700 Gevent3. We can wake + * up the system by pressing the key. + */ + Method (SIOS, 1) + { + /* We only enable KBD PME for S5. */ + If (LLess (Arg0, 0x05)) + { + EPNP() + /* DBGO("8718F\n") */ + + Store (0x4, LDN) + Store (One, ACTR) /* Enable EC */ + /* + Store (0x4, LDN) + Store (0x04, APC4) + */ /* falling edge. which mode? Not sure. */ + + Store (0x4, LDN) + Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ + Store (0x4, LDN) + Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ + + XPNP() + } + } + Method (SIOW, 1) + { + EPNP() + Store (0x4, LDN) + Store (Zero, APC0) /* disable keyboard PME */ + Store (0x4, LDN) + Store (0xFF, APC1) /* clear keyboard PME status */ + XPNP() + } + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ + + /* DRAM Memory from 1MB to TopMem */ + Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ + + /* BIOS space just below 4GB */ + DWORDMemory( + ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PCBM + ) + + /* DRAM memory from 4GB to TopMem2 */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + DMHI + ) + + /* BIOS space just below 16EB */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000001, /* Max-Min, RLEN */ + ,, + PEBM + ) + + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\_SB\PCI0\_CRS\n") */ + + CreateDWordField(CRES, ^EMM1._BAS, EM1B) + CreateDWordField(CRES, ^EMM1._LEN, EM1L) + CreateDWordField(CRES, ^DMLO._BAS, DMLB) + CreateDWordField(CRES, ^DMLO._LEN, DMLL) + CreateDWordField(CRES, ^PCBM._MIN, PBMB) + CreateDWordField(CRES, ^PCBM._LEN, PBML) + + CreateQWordField(CRES, ^DMHI._MIN, DMHB) + CreateQWordField(CRES, ^DMHI._LEN, DMHL) + CreateQWordField(CRES, ^PEBM._MIN, EBMB) + CreateQWordField(CRES, ^PEBM._LEN, EBML) + + If(LGreater(LOMH, 0xC0000)){ + Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ + Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ + } + + /* Set size of memory from 1MB to TopMem */ + Subtract(TOM1, 0x100000, DMLL) + + /* + * If(LNotEqual(TOM2, 0x00000000)){ + * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) + * } + */ + + /* If there is no memory above 4GB, put the BIOS just below 4GB */ + If(LEqual(TOM2, 0x00000000)){ + Store(PBAD,PBMB) /* Reserve the "BIOS" space */ + Store(PBLN,PBML) + } + Else { /* Otherwise, put the BIOS just below 16EB */ + ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ + Store(PBLN,EBML) + } + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + + /* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ + Method(_INI, 0) { + /* DBGO("\_SB\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \_OS=") */ + /* DBGO(_OS) */ + /* DBGO("\n \_REV=") */ + /* DBGO(_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ + } /* End Method(_SB._INI) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End _SB scope */ + + Scope(_SI) { + Method(_SST, 1) { + /* DBGO("\_SI\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ + + /* SMBUS Support */ + Mutex (SBX0, 0x00) + OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) + Field (SMB0, ByteAcc, NoLock, Preserve) { + HSTS, 8, /* SMBUS status */ + SSTS, 8, /* SMBUS slave status */ + HCNT, 8, /* SMBUS control */ + HCMD, 8, /* SMBUS host cmd */ + HADD, 8, /* SMBUS address */ + DAT0, 8, /* SMBUS data0 */ + DAT1, 8, /* SMBUS data1 */ + BLKD, 8, /* SMBUS block data */ + SCNT, 8, /* SMBUS slave control */ + SCMD, 8, /* SMBUS shaow cmd */ + SEVT, 8, /* SMBUS slave event */ + SDAT, 8 /* SMBUS slave data */ + } + + Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ + Store (0x1E, HSTS) + Store (0xFA, Local0) + While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { + Stall (0x64) + Decrement (Local0) + } + + Return (Local0) + } + + Method (SWTC, 1, NotSerialized) { + Store (Arg0, Local0) + Store (0x07, Local2) + Store (One, Local1) + While (LEqual (Local1, One)) { + Store (And (HSTS, 0x1E), Local3) + If (LNotEqual (Local3, Zero)) { /* read sucess */ + If (LEqual (Local3, 0x02)) { + Store (Zero, Local2) + } + + Store (Zero, Local1) + } + Else { + If (LLess (Local0, 0x0A)) { /* read failure */ + Store (0x10, Local2) + Store (Zero, Local1) + } + Else { + Sleep (0x0A) /* 10 ms, try again */ + Subtract (Local0, 0x0A, Local0) + } + } + } + + Return (Local2) + } + + Method (SMBR, 3, NotSerialized) { + Store (0x07, Local0) + If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { + Store (WCLR (), Local0) /* clear SMBUS status register before read data */ + If (LEqual (Local0, Zero)) { + Release (SBX0) + Return (0x0) + } + + Store (0x1F, HSTS) + Store (Or (ShiftLeft (Arg1, One), One), HADD) + Store (Arg2, HCMD) + If (LEqual (Arg0, 0x07)) { + Store (0x48, HCNT) /* read byte */ + } + + Store (SWTC (0x03E8), Local1) /* 1000 ms */ + If (LEqual (Local1, Zero)) { + If (LEqual (Arg0, 0x07)) { + Store (DAT0, Local0) + } + } + Else { + Store (Local1, Local0) + } + + Release (SBX0) + } + + /* DBGO("the value of SMBusData0 register ") */ + /* DBGO(Arg2) */ + /* DBGO(" is ") */ + /* DBGO(Local0) */ + /* DBGO("\n") */ + + Return (Local0) + } + + /* THERMAL */ + Scope(_TZ) { + Name (KELV, 2732) + Name (THOT, 800) + Name (TCRT, 850) + + ThermalZone(TZ00) { + Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ + /* DBGO("\_TZ\TZ00\_AC0\n") */ + Return(Add(0, 2730)) + } + Method(_AL0,0) { /* Returns package of cooling device to turn on */ + /* DBGO("\_TZ\TZ00\_AL0\n") */ + Return(Package() {_TZ.TZ00.FAN0}) + } + Device (FAN0) { + Name(_HID, EISAID("PNP0C0B")) + Name(_PR0, Package() {PFN0}) + } + + PowerResource(PFN0,0,0) { + Method(_STA) { + Store(0xF,Local0) + Return(Local0) + } + Method(_ON) { + /* DBGO("\_TZ\TZ00\FAN0 _ON\n") */ + } + Method(_OFF) { + /* DBGO("\_TZ\TZ00\FAN0 _OFF\n") */ + } + } + + Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ + /* DBGO("\_TZ\TZ00\_HOT\n") */ + Return (Add (THOT, KELV)) + } + Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ + /* DBGO("\_TZ\TZ00\_CRT\n") */ + Return (Add (TCRT, KELV)) + } + Method(_TMP,0) { /* return current temp of this zone */ + Store (SMBR (0x07, 0x4C,, 0x00), Local0) + If (LGreater (Local0, 0x10)) { + Store (Local0, Local1) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400, KELV)) + } + + Store (SMBR (0x07, 0x4C, 0x01), Local0) + /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ + /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ + If (LGreater (Local0, 0x10)) { + If (LGreater (Local0, Local1)) { + Store (Local0, Local1) + } + + Multiply (Local1, 10, Local1) + Return (Add (Local1, KELV)) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400 , KELV)) + } + } /* end of _TMP */ + } /* end of TZ00 */ + } +} +/* End of ASL file */ diff --git a/src/mainboard/asus/m4a785t-m/get_bus_conf.c b/src/mainboard/asus/m4a785t-m/get_bus_conf.c new file mode 100644 index 0000000..577b51c --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/get_bus_conf.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli GNUtoo@no-log.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/get_bus_conf.c" diff --git a/src/mainboard/asus/m4a785t-m/irq_tables.c b/src/mainboard/asus/m4a785t-m/irq_tables.c new file mode 100644 index 0000000..b4c030f --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/irq_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli GNUtoo@no-log.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/irq_tables.c" diff --git a/src/mainboard/asus/m4a785t-m/mainboard.c b/src/mainboard/asus/m4a785t-m/mainboard.c new file mode 100644 index 0000000..76a2a68 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/mainboard.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli GNUtoo@no-log.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/mainboard.c" diff --git a/src/mainboard/asus/m4a785t-m/mptable.c b/src/mainboard/asus/m4a785t-m/mptable.c new file mode 100644 index 0000000..c6e4b88 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/mptable.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli GNUtoo@no-log.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/mptable.c" diff --git a/src/mainboard/asus/m4a785t-m/romstage.c b/src/mainboard/asus/m4a785t-m/romstage.c new file mode 100644 index 0000000..43cd523 --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/romstage.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Denis 'GNUtoo' Carikli GNUtoo@no-log.org + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "../m4a785-m/romstage.c"
Am Sonntag, den 27.11.2011, 18:59 +0100 schrieb Denis Carikli:
Denis Carikli (GNUtoo@no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/457
-gerrit
commit 1eb55d026f9d364eb8f3d7ededc4dc7f98deafef Author: Denis 'GNUtoo' Carikli GNUtoo@no-log.org Date: Sun Nov 27 15:58:38 2011 +0100
Add ASUS M4A785T-M mainboard support This mainboard is very similar to the M4A785-M, but it has DDR3 instead of DDR2. That's why most of the code was copied or included from the m4a785-m directory Notable changes between the two mainboards include: * the selection of the last microcode (mc_patch_010000b6.h) which made it pass the CPU init. * the selection of DDR3 which made it pass the ram init
Thank you very much for the patch.
Could you add what you have tested and not, what works and what does not (flickering)? The OS you tested with. You need to add pci=nocrs currently to the command line if I remember correctly.
You have a Wiki page already. Could you add the URL to this page too? Also URLs to messages in the list archives with the boot log and for example `dmesg`.
Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
[…]
Thanks,
Paul
here's dmesg: [ 0.000000] Initializing cgroup subsys cpuset [ 0.000000] Initializing cgroup subsys cpu [ 0.000000] Linux version 2.6.38-12-generic (root@devel.trisquel.info) (gcc version 4.5.2 (Ubuntu/Linaro 4.5.2-8ubuntu4) ) #0trisquel1 SMP Tue Oct 25 15:17:30 UTC 2011 (Ubuntu 2.6.38-12.51+5.0trisquel1-generic 2.6.38.8-libre) [ 0.000000] BIOS-provided physical RAM map: [ 0.000000] BIOS-e820: 0000000000000000 - 000000000009f800 (usable) [ 0.000000] BIOS-e820: 000000000009f800 - 00000000000a0000 (reserved) [ 0.000000] BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved) [ 0.000000] BIOS-e820: 0000000000100000 - 000000006ffee000 (usable) [ 0.000000] BIOS-e820: 000000006ffee000 - 0000000080000000 (reserved) [ 0.000000] BIOS-e820: 00000000e0000000 - 00000000f0000000 (reserved) [ 0.000000] BIOS-e820: 00000000fec00000 - 00000000fec01000 (reserved) [ 0.000000] BIOS-e820: 00000000fed00000 - 00000000fed00400 (reserved) [ 0.000000] Notice: NX (Execute Disable) protection cannot be enabled in hardware: non-PAE kernel! [ 0.000000] NX (Execute Disable) protection: approximated by x86 segment limits [ 0.000000] DMI present. [ 0.000000] DMI: ASUS M4A785T-M, BIOS 4.0-1889-gac9f320 11/27/2011 [ 0.000000] e820 update range: 0000000000000000 - 0000000000010000 (usable) ==> (reserved) [ 0.000000] e820 remove range: 00000000000a0000 - 0000000000100000 (usable) [ 0.000000] last_pfn = 0x6ffee max_arch_pfn = 0x100000 [ 0.000000] MTRR default type: uncachable [ 0.000000] MTRR fixed ranges enabled: [ 0.000000] 00000-9FFFF write-back [ 0.000000] A0000-BFFFF uncachable [ 0.000000] C0000-FFFFF write-back [ 0.000000] MTRR variable ranges enabled: [ 0.000000] 0 base 000000000000 mask FFFF80000000 write-back [ 0.000000] 1 base 000070000000 mask FFFFF0000000 uncachable [ 0.000000] 2 disabled [ 0.000000] 3 disabled [ 0.000000] 4 disabled [ 0.000000] 5 disabled [ 0.000000] 6 disabled [ 0.000000] 7 disabled [ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106 [ 0.000000] found SMP MP-table at [c00fd980] fd980 [ 0.000000] initial memory mapped : 0 - 01c00000 [ 0.000000] init_memory_mapping: 0000000000000000-00000000377fe000 [ 0.000000] 0000000000 - 0000400000 page 4k [ 0.000000] 0000400000 - 0037400000 page 2M [ 0.000000] 0037400000 - 00377fe000 page 4k [ 0.000000] kernel direct mapping tables up to 377fe000 @ 1bfb000-1c00000 [ 0.000000] RAMDISK: 35fd6000 - 36fe3000 [ 0.000000] ACPI: RSDP 000fd960 00014 (v00 CORE ) [ 0.000000] ACPI: RSDT 6fff2424 0003C (v01 CORE COREBOOT 00000000 CORE 00000000) [ 0.000000] ACPI: HPET 6fff24c8 00038 (v01 CORE COREBOOT 00000000 CORE 00000000) [ 0.000000] ACPI: APIC 6fff2500 0005C (v01 CORE COREBOOT 00000000 CORE 00000000) [ 0.000000] ACPI: SRAT 6fff2560 000A0 (v01 CORE COREBOOT 00000000 CORE 00000000) [ 0.000000] ACPI: SLIT 6fff2600 0002D (v01 CORE COREBOOT 00000000 CORE 00000000) [ 0.000000] ACPI: SSDT 6fff2630 00635 (v01 AMD-FA AMD-ACPI 06040000 INTL 20110922) [ 0.000000] ACPI: FACP 6fff56c0 000F4 (v03 CORE COREBOOT 00000000 CORE 00000000) [ 0.000000] ACPI: DSDT 6fff2c68 02A18 (v02 ASUS M4A785-M 00010001 INTL 20110922) [ 0.000000] ACPI: FACS 6fff5680 00040 [ 0.000000] ACPI: Local APIC address 0xfee00000 [ 0.000000] 903MB HIGHMEM available. [ 0.000000] 887MB LOWMEM available. [ 0.000000] mapped low ram: 0 - 377fe000 [ 0.000000] low ram: 0 - 377fe000 [ 0.000000] Zone PFN ranges: [ 0.000000] DMA 0x00000010 -> 0x00001000 [ 0.000000] Normal 0x00001000 -> 0x000377fe [ 0.000000] HighMem 0x000377fe -> 0x0006ffee [ 0.000000] Movable zone start PFN for each node [ 0.000000] early_node_map[2] active PFN ranges [ 0.000000] 0: 0x00000010 -> 0x0000009f [ 0.000000] 0: 0x00000100 -> 0x0006ffee [ 0.000000] On node 0 totalpages: 458621 [ 0.000000] free_area_init_node: node 0, pgdat c1770140, node_mem_map f51d6200 [ 0.000000] DMA zone: 32 pages used for memmap [ 0.000000] DMA zone: 0 pages reserved [ 0.000000] DMA zone: 3951 pages, LIFO batch:0 [ 0.000000] Normal zone: 1744 pages used for memmap [ 0.000000] Normal zone: 221486 pages, LIFO batch:31 [ 0.000000] HighMem zone: 1808 pages used for memmap [ 0.000000] HighMem zone: 229600 pages, LIFO batch:31 [ 0.000000] Using APIC driver default [ 0.000000] ACPI: PM-Timer IO Port: 0x818 [ 0.000000] ACPI: Local APIC address 0xfee00000 [ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled) [ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled) [ 0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0]) [ 0.000000] IOAPIC[0]: apic_id 2, version 33, address 0xfec00000, GSI 0-23 [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) [ 0.000000] ACPI: IRQ0 used by override. [ 0.000000] ACPI: IRQ2 used by override. [ 0.000000] ACPI: IRQ9 used by override. [ 0.000000] Using ACPI (MADT) for SMP configuration information [ 0.000000] ACPI: HPET id: 0x102282a0 base: 0xfed00000 [ 0.000000] SMP: Allowing 2 CPUs, 0 hotplug CPUs [ 0.000000] nr_irqs_gsi: 40 [ 0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000 [ 0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000f0000 [ 0.000000] PM: Registered nosave memory: 00000000000f0000 - 0000000000100000 [ 0.000000] Allocating PCI resources starting at 80000000 (gap: 80000000:60000000) [ 0.000000] Booting paravirtualized kernel on bare hardware [ 0.000000] setup_percpu: NR_CPUS:8 nr_cpumask_bits:8 nr_cpu_ids:2 nr_node_ids:1 [ 0.000000] PERCPU: Embedded 13 pages/cpu @f7000000 s28800 r0 d24448 u2097152 [ 0.000000] pcpu-alloc: s28800 r0 d24448 u2097152 alloc=1*4194304 [ 0.000000] pcpu-alloc: [0] 0 1 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 455037 [ 0.000000] Kernel command line: BOOT_IMAGE=/vmlinuz-2.6.38-12-generic root=/dev/mapper/root ro console=ttyS0,115200 console=tty0 modeset=1 pci=nocrs [ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes) [ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) [ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) [ 0.000000] Initializing CPU#0 [ 0.000000] allocated 9174360 bytes of page_cgroup [ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups [ 0.000000] Initializing HighMem for node 0 (000377fe:0006ffee) [ 0.000000] Memory: 1784528k/1834936k available (5190k kernel code, 49956k reserved, 2458k data, 700k init, 925632k highmem) [ 0.000000] virtual kernel memory layout: [ 0.000000] fixmap : 0xfff16000 - 0xfffff000 ( 932 kB) [ 0.000000] pkmap : 0xff800000 - 0xffc00000 (4096 kB) [ 0.000000] vmalloc : 0xf7ffe000 - 0xff7fe000 ( 120 MB) [ 0.000000] lowmem : 0xc0000000 - 0xf77fe000 ( 887 MB) [ 0.000000] .init : 0xc1779000 - 0xc1828000 ( 700 kB) [ 0.000000] .data : 0xc1511b51 - 0xc17784c0 (2458 kB) [ 0.000000] .text : 0xc1000000 - 0xc1511b51 (5190 kB) [ 0.000000] Checking if this processor honours the WP bit even in supervisor mode...Ok. [ 0.000000] SLUB: Genslabs=15, HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 [ 0.000000] Hierarchical RCU implementation. [ 0.000000] RCU dyntick-idle grace-period acceleration is enabled. [ 0.000000] RCU-based detection of stalled CPUs is disabled. [ 0.000000] NR_IRQS:2304 nr_irqs:512 16 [ 0.000000] CPU 0 irqstacks, hard=f4408000 soft=f440a000 [ 0.000000] spurious 8259A interrupt: IRQ7. [ 0.000000] Console: colour VGA+ 80x25 [ 0.000000] console [tty0] enabled [ 0.000000] console [ttyS0] enabled [ 0.000000] hpet clockevent registered [ 0.000000] Fast TSC calibration using PIT [ 0.000000] Detected 3000.540 MHz processor. [ 0.012002] Calibrating delay loop (skipped), value calculated using timer frequency.. 6001.08 BogoMIPS (lpj=12002160) [ 0.020006] pid_max: default: 32768 minimum: 301 [ 0.024023] Security Framework initialized [ 0.028018] AppArmor: AppArmor initialized [ 0.032005] Yama: becoming mindful. [ 0.036056] Mount-cache hash table entries: 512 [ 0.040107] Initializing cgroup subsys ns [ 0.044008] ns_cgroup deprecated: consider using the 'clone_children' flag without the ns_cgroup. [ 0.048007] Initializing cgroup subsys cpuacct [ 0.052008] Initializing cgroup subsys memory [ 0.056013] Initializing cgroup subsys devices [ 0.060010] Initializing cgroup subsys freezer [ 0.064007] Initializing cgroup subsys net_cls [ 0.068006] Initializing cgroup subsys blkio [ 0.072032] CPU: Physical Processor ID: 0 [ 0.076007] CPU: Processor Core ID: 0 [ 0.080009] mce: CPU supports 6 MCE banks [ 0.089049] ACPI: Core revision 20110112 [ 0.094004] ftrace: allocating 23652 entries in 47 pages [ 0.100066] Enabling APIC mode: Flat. Using 1 I/O APICs [ 0.108648] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 [ 0.154477] CPU0: AMD Athlon(tm) II X2 250 Processor stepping 02 [ 0.164009] Performance Events: AMD PMU driver. [ 0.164012] ... version: 0 [ 0.168010] ... bit width: 48 [ 0.172010] ... generic registers: 4 [ 0.176011] ... value mask: 0000ffffffffffff [ 0.180011] ... max period: 00007fffffffffff [ 0.184011] ... fixed-purpose events: 0 [ 0.188012] ... event mask: 000000000000000f [ 0.192410] CPU 1 irqstacks, hard=f44aa000 soft=f44ac000 [ 0.192414] Booting Node 0, Processors #1 Ok. [ 0.012000] Initializing CPU#1 [ 0.292017] TSC synchronization [CPU#0 -> CPU#1]: [ 0.292017] Measured 37471011521 cycles TSC warp between CPUs, turning off TSC clock. [ 0.292017] Marking TSC unstable due to check_tsc_sync_source failed [ 0.292026] Brought up 2 CPUs [ 0.296019] Total of 2 processors activated (10001.42 BogoMIPS). [ 0.300851] devtmpfs: initialized [ 0.308517] print_constraints: dummy: [ 0.312055] Time: 4:11:53 Date: 11/28/11 [ 0.316071] NET: Registered protocol family 16 [ 0.320059] Trying to unpack rootfs image as initramfs... [ 0.320179] EISA bus registered [ 0.320187] node 0 link 0: io port [1000, 3fff] [ 0.320192] TOM: 0000000080000000 aka 2048M [ 0.320195] Fam 10h mmconf [e0000000, efffffff] [ 0.320200] node 0 link 0: mmio [d4000000, d84fffff] [ 0.320204] node 0 link 0: mmio [c0000000, d00fffff] [ 0.320209] bus: [00, 03] on node 0 link 0 [ 0.320213] bus: 00 index 0 [io 0x0000-0xffff] [ 0.320217] bus: 00 index 1 [mem 0xd0100000-0xdfffffff] [ 0.320221] bus: 00 index 2 [mem 0x80000000-0xd00fffff] [ 0.320224] bus: 00 index 3 [mem 0xf0000000-0xffffffff] [ 0.320253] Extended Config Space enabled on 1 nodes [ 0.320263] ACPI: bus type pci registered [ 0.320463] PCI: PCI BIOS revision 2.10 entry at 0xfc839, last bus=3 [ 0.320466] PCI: Using configuration type 1 for base access [ 0.320468] PCI: Using configuration type 1 for extended access [ 0.320492] mtrr: your CPUs had inconsistent variable MTRR settings [ 0.320494] mtrr: probably your BIOS does not setup all CPUs. [ 0.320496] mtrr: corrected configuration. [ 0.320496] bio: create slab <bio-0> at 0 [ 0.321495] ACPI: EC: Look up EC in DSDT [ 0.321495] ACPI: Executed 2 blocks of module-level executable AML code [ 0.321495] ACPI: Interpreter enabled [ 0.328024] ACPI: (supports S0 S1 S2 S3 S4 S5) [ 0.333620] ACPI: BIOS offers _BFS [ 0.336023] ACPI: If "acpi.bfs=1" improves resume, please notify linux- acpi@vger.kernel.org [ 0.348024] ACPI: Using IOAPIC for interrupt routing [ 0.377796] ACPI: Power Resource [PFN0] (on) [ 0.412155] ACPI: No dock devices found. [ 0.416028] HEST: Table not found. [ 0.418382] PCI: Ignoring host bridge windows from ACPI; if necessary, use "pci=use_crs" and report a bug [ 0.428130] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.437523] ACPI Error: Method parse/execution failed [_SB_.PCI0._CRS] (Node f4426e70), AE_NOT_FOUND (20110112/psparse-536) [ 0.448036] [Firmware Bug]: ACPI: no secondary bus range in _CRS [ 0.456041] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) [ 0.464166] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.469530] ACPI Error: Method parse/execution failed [_SB_.PCI0._CRS] (Node f4426e70), AE_NOT_FOUND (20110112/psparse-536) [ 0.482505] pci 0000:00:00.0: [1022:9601] type 0 class 0x000600 [ 0.482652] pci 0000:00:01.0: [1022:9602] type 1 class 0x000604 [ 0.484130] pci 0000:00:0a.0: [1022:9609] type 1 class 0x000604 [ 0.484219] pci 0000:00:0a.0: PME# supported from D0 D3hot D3cold [ 0.484226] pci 0000:00:0a.0: PME# disabled [ 0.484280] pci 0000:00:11.0: [1002:4390] type 0 class 0x000101 [ 0.484314] pci 0000:00:11.0: reg 10: [io 0x3020-0x3027] [ 0.484331] pci 0000:00:11.0: reg 14: [io 0x3040-0x3043] [ 0.484347] pci 0000:00:11.0: reg 18: [io 0x3028-0x302f] [ 0.484363] pci 0000:00:11.0: reg 1c: [io 0x3044-0x3047] [ 0.484382] pci 0000:00:11.0: reg 20: [io 0x3000-0x300f] [ 0.484399] pci 0000:00:11.0: reg 24: [mem 0xd8409000-0xd84093ff] [ 0.484437] pci 0000:00:11.0: set SATA to AHCI mode [ 0.488090] pci 0000:00:12.0: [1002:4397] type 0 class 0x000c03 [ 0.488113] pci 0000:00:12.0: reg 10: [mem 0xd8404000-0xd8404fff] [ 0.488224] pci 0000:00:12.1: [1002:4398] type 0 class 0x000c03 [ 0.488252] pci 0000:00:12.1: reg 10: [mem 0xd8405000-0xd8405fff] [ 0.488370] pci 0000:00:12.2: [1002:4396] type 0 class 0x000c03 [ 0.488407] pci 0000:00:12.2: reg 10: [mem 0xd8409400-0xd84094ff] [ 0.488528] pci 0000:00:12.2: supports D1 D2 [ 0.488532] pci 0000:00:12.2: PME# supported from D0 D1 D2 D3hot [ 0.488538] pci 0000:00:12.2: PME# disabled [ 0.488576] pci 0000:00:13.0: [1002:4397] type 0 class 0x000c03 [ 0.488597] pci 0000:00:13.0: reg 10: [mem 0xd8406000-0xd8406fff] [ 0.488712] pci 0000:00:13.1: [1002:4398] type 0 class 0x000c03 [ 0.488736] pci 0000:00:13.1: reg 10: [mem 0xd8407000-0xd8407fff] [ 0.488855] pci 0000:00:13.2: [1002:4396] type 0 class 0x000c03 [ 0.488891] pci 0000:00:13.2: reg 10: [mem 0xd8409500-0xd84095ff] [ 0.489013] pci 0000:00:13.2: supports D1 D2 [ 0.489017] pci 0000:00:13.2: PME# supported from D0 D1 D2 D3hot [ 0.489024] pci 0000:00:13.2: PME# disabled [ 0.489067] pci 0000:00:14.0: [1002:4385] type 0 class 0x000c05 [ 0.489209] pci 0000:00:14.1: [1002:439c] type 0 class 0x000101 [ 0.489227] pci 0000:00:14.1: reg 10: [io 0x3030-0x3037] [ 0.489245] pci 0000:00:14.1: reg 14: [io 0x3048-0x304b] [ 0.489258] pci 0000:00:14.1: reg 18: [io 0x3038-0x303f] [ 0.489271] pci 0000:00:14.1: reg 1c: [io 0x304c-0x304f] [ 0.489284] pci 0000:00:14.1: reg 20: [io 0x3010-0x301f] [ 0.489336] pci 0000:00:14.2: [1002:4383] type 0 class 0x000403 [ 0.489371] pci 0000:00:14.2: reg 10: [mem 0xd8400000-0xd8403fff 64bit] [ 0.489449] pci 0000:00:14.2: PME# supported from D0 D3hot D3cold [ 0.489455] pci 0000:00:14.2: PME# disabled [ 0.489478] pci 0000:00:14.3: [1002:439d] type 0 class 0x000601 [ 0.489584] pci 0000:00:14.4: [1002:4384] type 1 class 0x000604 [ 0.492072] pci 0000:00:14.5: [1002:4399] type 0 class 0x000c03 [ 0.492090] pci 0000:00:14.5: reg 10: [mem 0xd8408000-0xd8408fff] [ 0.492184] pci 0000:00:18.0: [1022:1200] type 0 class 0x000600 [ 0.492211] pci 0000:00:18.1: [1022:1201] type 0 class 0x000600 [ 0.492234] pci 0000:00:18.2: [1022:1202] type 0 class 0x000600 [ 0.492258] pci 0000:00:18.3: [1022:1203] type 0 class 0x000600 [ 0.492284] pci 0000:00:18.4: [1022:1204] type 0 class 0x000600 [ 0.492318] PCI: peer root bus 00 res updated from pci conf [ 0.492375] pci 0000:01:05.0: [1002:9710] type 0 class 0x000300 [ 0.492393] pci 0000:01:05.0: reg 10: [mem 0xc0000000-0xcfffffff pref] [ 0.492403] pci 0000:01:05.0: reg 14: [io 0x1000-0x10ff] [ 0.492413] pci 0000:01:05.0: reg 18: [mem 0xd8100000-0xd810ffff] [ 0.492441] pci 0000:01:05.0: reg 24: [mem 0xd8000000-0xd80fffff] [ 0.492466] pci 0000:01:05.0: supports D1 D2 [ 0.492491] pci 0000:01:05.1: [1002:970f] type 0 class 0x000403 [ 0.492508] pci 0000:01:05.1: reg 10: [mem 0xd8110000-0xd8113fff] [ 0.492570] pci 0000:01:05.1: supports D1 D2 [ 0.492634] pci 0000:00:01.0: PCI bridge to [bus 01-01] [ 0.496038] pci 0000:00:01.0: bridge window [io 0x1000-0x1fff] [ 0.496044] pci 0000:00:01.0: bridge window [mem 0xd8000000-0xd81fffff] [ 0.496053] pci 0000:00:01.0: bridge window [mem 0xc0000000-0xcfffffff 64bit pref] [ 0.496152] pci 0000:02:00.0: [10ec:8168] type 0 class 0x000200 [ 0.496173] pci 0000:02:00.0: reg 10: [io 0x2000-0x20ff] [ 0.496217] pci 0000:02:00.0: reg 18: [mem 0xd0004000-0xd0004fff 64bit pref] [ 0.496244] pci 0000:02:00.0: reg 20: [mem 0xd0000000-0xd0003fff 64bit pref] [ 0.496260] pci 0000:02:00.0: reg 30: [mem 0xd8200000-0xd820ffff pref] [ 0.496312] pci 0000:02:00.0: supports D1 D2 [ 0.496316] pci 0000:02:00.0: PME# supported from D0 D1 D2 D3hot D3cold [ 0.496323] pci 0000:02:00.0: PME# disabled [ 0.496389] pci 0000:00:0a.0: PCI bridge to [bus 02-02] [ 0.504044] pci 0000:00:0a.0: bridge window [io 0x2000-0x2fff] [ 0.504051] pci 0000:00:0a.0: bridge window [mem 0xd8200000-0xd82fffff] [ 0.504060] pci 0000:00:0a.0: bridge window [mem 0xd0000000-0xd00fffff 64bit pref] [ 0.504115] pci 0000:03:06.0: [168c:0029] type 0 class 0x000280 [ 0.504146] pci 0000:03:06.0: reg 10: [mem 0xd8300000-0xd830ffff] [ 0.504279] pci 0000:03:06.0: PME# supported from D0 D3hot [ 0.504287] pci 0000:03:06.0: PME# disabled [ 0.504355] pci 0000:00:14.4: PCI bridge to [bus 03-03] (subtractive decode) [ 0.512037] pci 0000:00:14.4: bridge window [io 0xf000-0xe000] (disabled) [ 0.512044] pci 0000:00:14.4: bridge window [mem 0xd8300000-0xd83fffff] [ 0.512052] pci 0000:00:14.4: bridge window [mem 0xdff00000-0xdfefffff pref] (disabled) [ 0.512057] pci 0000:00:14.4: bridge window [io 0x0000-0xffff] (subtractive decode) [ 0.512062] pci 0000:00:14.4: bridge window [mem 0xd0100000-0xdfffffff] (subtractive decode) [ 0.512067] pci 0000:00:14.4: bridge window [mem 0x80000000-0xd00fffff] (subtractive decode) [ 0.512072] pci 0000:00:14.4: bridge window [mem 0xf0000000-0xffffffff] (subtractive decode) [ 0.512090] pci_bus 0000:00: on NUMA node 0 [ 0.512095] ACPI: PCI Interrupt Routing Table [_SB_.PCI0._PRT] [ 0.512095] ACPI: PCI Interrupt Routing Table [_SB_.PCI0.AGPB._PRT] [ 0.512105] ACPI: PCI Interrupt Routing Table [_SB_.PCI0.PBRA._PRT] [ 0.512149] ACPI: PCI Interrupt Routing Table [_SB_.PCI0.PIBR._PRT] [ 0.512282] pci0000:00: Requesting ACPI _OSC control (0x1d) [ 0.528310] ACPI: PCI Interrupt Link [INTA] (IRQs 3 4 5 7 10 11 12 15) *0, disabled. [ 0.537025] ACPI: PCI Interrupt Link [INTB] (IRQs 3 4 5 7 10 11 12 15) *0, disabled. [ 0.545785] ACPI: PCI Interrupt Link [INTC] (IRQs 3 4 5 7 10 11 12 15) *0, disabled. [ 0.556305] ACPI: PCI Interrupt Link [INTD] (IRQs 3 4 5 7 10 11 12 15) *0, disabled. [ 0.565026] ACPI: PCI Interrupt Link [INTE] (IRQs 3 4 5 7 10 11 12 15) *0, disabled. [ 0.573907] ACPI: PCI Interrupt Link [INTF] (IRQs 9) *0, disabled. [ 0.581417] ACPI: PCI Interrupt Link [INTG] (IRQs 3 4 5 7 10 11 12 15) *0, disabled. [ 0.590178] ACPI: PCI Interrupt Link [INTH] (IRQs 3 4 5 7 10 11 12 15) *0, disabled. [ 0.600395] vgaarb: device added: PCI:0000:01:05.0,decodes=io+mem,owns=io+mem,locks=none [ 0.608043] vgaarb: loaded [ 0.612323] SCSI subsystem initialized [ 0.617817] Freeing initrd memory: 16436k freed [ 0.617817] libata version 3.00 loaded. [ 0.617817] usbcore: registered new interface driver usbfs [ 0.617817] usbcore: registered new interface driver hub [ 0.617817] usbcore: registered new device driver usb [ 0.617817] wmi: Mapper loaded [ 0.617817] PCI: Using ACPI for IRQ routing [ 0.617817] PCI: pci_cache_line_size set to 64 bytes [ 0.617817] reserve RAM buffer: 000000000009f800 - 000000000009ffff [ 0.617817] reserve RAM buffer: 000000006ffee000 - 000000006fffffff [ 0.617817] NetLabel: Initializing [ 0.617817] NetLabel: domain hash size = 128 [ 0.617817] NetLabel: protocols = UNLABELED CIPSOv4 [ 0.617817] NetLabel: unlabeled traffic allowed by default [ 0.617817] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0 [ 0.617817] hpet0: 4 comparators, 32-bit 14.318180 MHz counter [ 0.618190] Switching to clocksource hpet [ 0.626218] Switched to NOHz mode on CPU #0 [ 0.627160] Switched to NOHz mode on CPU #1 [ 0.637951] AppArmor: AppArmor Filesystem Enabled [ 0.643804] pnp: PnP ACPI init [ 0.647038] ACPI: bus type pnp registered [ 0.651436] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.660501] ACPI Error: Method parse/execution failed [_SB_.PCI0._CRS] (Node f4426e70), AE_NOT_FOUND (20110112/psparse-536) [ 0.672470] pnp 00:00: Plug and Play ACPI device, IDs PNP0a03 (active) [ 0.672640] pnp 00:01: [irq 8] [ 0.672645] pnp 00:01: [io 0x0070-0x0071] [ 0.672698] pnp 00:01: Plug and Play ACPI device, IDs PNP0b00 (active) [ 0.672714] pnp 00:02: [io 0x0061] [ 0.672767] pnp 00:02: Plug and Play ACPI device, IDs PNP0800 (active) [ 0.672785] pnp 00:03: [dma 4] [ 0.672788] pnp 00:03: [io 0x0000-0x000f] [ 0.672793] pnp 00:03: [io 0x0081-0x0083] [ 0.672797] pnp 00:03: [io 0x0087] [ 0.672800] pnp 00:03: [io 0x0089-0x008b] [ 0.672803] pnp 00:03: [io 0x008f] [ 0.672807] pnp 00:03: [io 0x00c0-0x00df] [ 0.672862] pnp 00:03: Plug and Play ACPI device, IDs PNP0200 (active) [ 0.672876] pnp 00:04: [io 0x00f0-0x00ff] [ 0.672887] pnp 00:04: [irq 13] [ 0.672941] pnp 00:04: Plug and Play ACPI device, IDs PNP0c04 (active) [ 0.672985] pnp 00:05: [mem 0xfed00000-0xfed003ff] [ 0.673039] pnp 00:05: Plug and Play ACPI device, IDs PNP0103 (active) [ 0.673067] pnp: PnP ACPI: found 6 devices [ 0.677642] ACPI: ACPI bus type pnp unregistered [ 0.682414] PnPBIOS: Disabled by ACPI PNP [ 0.724847] pci 0000:00:01.0: PCI bridge to [bus 01-01] [ 0.730586] pci 0000:00:01.0: bridge window [io 0x1000-0x1fff] [ 0.736784] pci 0000:00:01.0: bridge window [mem 0xd8000000-0xd81fffff] [ 0.743719] pci 0000:00:01.0: bridge window [mem 0xc0000000-0xcfffffff 64bit pref] [ 0.751632] pci 0000:00:0a.0: PCI bridge to [bus 02-02] [ 0.757013] pci 0000:00:0a.0: bridge window [io 0x2000-0x2fff] [ 0.763258] pci 0000:00:0a.0: bridge window [mem 0xd8200000-0xd82fffff] [ 0.770203] pci 0000:00:0a.0: bridge window [mem 0xd0000000-0xd00fffff 64bit pref] [ 0.778120] pci 0000:00:14.4: PCI bridge to [bus 03-03] [ 0.783494] pci 0000:00:14.4: bridge window [io disabled] [ 0.789268] pci 0000:00:14.4: bridge window [mem 0xd8300000-0xd83fffff] [ 0.796213] pci 0000:00:14.4: bridge window [mem pref disabled] [ 0.802489] pci 0000:00:0a.0: setting latency timer to 64 [ 0.802502] pci_bus 0000:00: resource 4 [io 0x0000-0xffff] [ 0.802507] pci_bus 0000:00: resource 5 [mem 0xd0100000-0xdfffffff] [ 0.802512] pci_bus 0000:00: resource 6 [mem 0x80000000-0xd00fffff] [ 0.802517] pci_bus 0000:00: resource 7 [mem 0xf0000000-0xffffffff] [ 0.802521] pci_bus 0000:01: resource 0 [io 0x1000-0x1fff] [ 0.802526] pci_bus 0000:01: resource 1 [mem 0xd8000000-0xd81fffff] [ 0.802530] pci_bus 0000:01: resource 2 [mem 0xc0000000-0xcfffffff 64bit pref] [ 0.802535] pci_bus 0000:02: resource 0 [io 0x2000-0x2fff] [ 0.802540] pci_bus 0000:02: resource 1 [mem 0xd8200000-0xd82fffff] [ 0.802544] pci_bus 0000:02: resource 2 [mem 0xd0000000-0xd00fffff 64bit pref] [ 0.802549] pci_bus 0000:03: resource 1 [mem 0xd8300000-0xd83fffff] [ 0.802554] pci_bus 0000:03: resource 4 [io 0x0000-0xffff] [ 0.802558] pci_bus 0000:03: resource 5 [mem 0xd0100000-0xdfffffff] [ 0.802562] pci_bus 0000:03: resource 6 [mem 0x80000000-0xd00fffff] [ 0.802567] pci_bus 0000:03: resource 7 [mem 0xf0000000-0xffffffff] [ 0.802617] NET: Registered protocol family 2 [ 0.807281] IP route cache hash table entries: 32768 (order: 5, 131072 bytes) [ 0.814922] TCP established hash table entries: 131072 (order: 8, 1048576 bytes) [ 0.823416] TCP bind hash table entries: 65536 (order: 7, 524288 bytes) [ 0.830997] TCP: Hash tables configured (established 131072 bind 65536) [ 0.837916] TCP reno registered [ 0.841201] UDP hash table entries: 512 (order: 2, 16384 bytes) [ 0.847274] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) [ 0.853854] NET: Registered protocol family 1 [ 0.858424] pci 0000:00:01.0: MSI quirk detected; subordinate MSI disabled [ 0.865582] pci 0000:01:05.0: Boot video device [ 0.865596] PCI: CLS 64 bytes, default 64 [ 0.865951] cpufreq-nforce2: No nForce2 chipset. [ 0.871126] audit: initializing netlink socket (disabled) [ 0.876776] type=2000 audit(1322453512.876:1): initialized [ 0.907042] highmem bounce pool size: 64 pages [ 0.911623] HugeTLB registered 4 MB page size, pre-allocated 0 pages [ 0.919507] VFS: Disk quotas dquot_6.5.2 [ 0.923670] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) [ 0.931933] fuse init (API version 7.16) [ 0.936066] msgmni has been set to 1709 [ 0.940445] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253) [ 0.948030] io scheduler noop registered [ 0.952079] io scheduler deadline registered [ 0.956518] io scheduler cfq registered (default) [ 0.961563] pcieport 0000:00:0a.0: setting latency timer to 64 [ 0.961641] pcieport 0000:00:0a.0: irq 40 for MSI/MSI-X [ 0.961780] pci_hotplug: PCI Hot Plug PCI Core version: 0.5 [ 0.967721] pciehp: PCI Express Hot Plug Controller Driver version: 0.4 [ 0.974651] input: Power Button as /devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0 [ 0.986284] ACPI: Power Button [PWRB] [ 0.990167] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1 [ 0.997773] ACPI: Power Button [PWRF] [ 1.001640] ACPI: Fan [FAN0] (on) [ 1.005350] ACPI: acpi_idle registered with cpuidle [ 1.028063] thermal LNXTHERM:00: registered as thermal_zone0 [ 1.033845] ACPI: Thermal Zone [TZ00] (40 C) [ 1.038211] ERST: Table is not found! [ 1.042063] isapnp: Scanning for PnP cards... [ 1.042087] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled [ 1.063191] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A [ 1.436173] isapnp: No Plug & Play device found [ 1.548255] Linux agpgart interface v0.103 [ 1.553492] brd: module loaded [ 1.557070] loop: module loaded [ 1.560414] i2c-core: driver [adp5520] using legacy suspend method [ 1.566723] i2c-core: driver [adp5520] using legacy resume method [ 1.572993] pata_acpi 0000:00:14.1: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 1.580617] Fixed MDIO Bus: probed [ 1.584124] PPP generic driver version 2.4.2 [ 1.588529] tun: Universal TUN/TAP device driver, 1.6 [ 1.593714] tun: (C) 1999-2004 Max Krasnyansky maxk@qualcomm.com [ 1.600084] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 1.606700] ehci_hcd 0000:00:12.2: PCI INT B -> GSI 17 (level, low) -> IRQ 17 [ 1.613971] ehci_hcd 0000:00:12.2: EHCI Host Controller [ 1.619306] ehci_hcd 0000:00:12.2: new USB bus registered, assigned bus number 1 [ 1.626899] ehci_hcd 0000:00:12.2: applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround [ 1.635806] ehci_hcd 0000:00:12.2: debug port 1 [ 1.640539] ehci_hcd 0000:00:12.2: irq 17, io mem 0xd8409400 [ 1.656029] ehci_hcd 0000:00:12.2: USB 2.0 started, EHCI 1.00 [ 1.662151] hub 1-0:1.0: USB hub found [ 1.666173] hub 1-0:1.0: 6 ports detected [ 1.670432] ehci_hcd 0000:00:13.2: PCI INT B -> GSI 19 (level, low) -> IRQ 19 [ 1.677812] ehci_hcd 0000:00:13.2: EHCI Host Controller [ 1.683249] ehci_hcd 0000:00:13.2: new USB bus registered, assigned bus number 2 [ 1.690853] ehci_hcd 0000:00:13.2: applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround [ 1.699723] ehci_hcd 0000:00:13.2: debug port 1 [ 1.704388] ehci_hcd 0000:00:13.2: irq 19, io mem 0xd8409500 [ 1.720025] ehci_hcd 0000:00:13.2: USB 2.0 started, EHCI 1.00 [ 1.725985] hub 2-0:1.0: USB hub found [ 1.729868] hub 2-0:1.0: 6 ports detected [ 1.734035] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver [ 1.740326] ohci_hcd 0000:00:12.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 1.747597] ohci_hcd 0000:00:12.0: OHCI Host Controller [ 1.752933] ohci_hcd 0000:00:12.0: new USB bus registered, assigned bus number 3 [ 1.760552] ohci_hcd 0000:00:12.0: irq 16, io mem 0xd8404000 [ 1.824176] hub 3-0:1.0: USB hub found [ 1.828109] hub 3-0:1.0: 3 ports detected [ 1.832314] ohci_hcd 0000:00:12.1: PCI INT A -> GSI 16 (level, low) -> IRQ 16 [ 1.839609] ohci_hcd 0000:00:12.1: OHCI Host Controller [ 1.845050] ohci_hcd 0000:00:12.1: new USB bus registered, assigned bus number 4 [ 1.852700] ohci_hcd 0000:00:12.1: irq 16, io mem 0xd8405000 [ 1.916086] hub 4-0:1.0: USB hub found [ 1.919909] hub 4-0:1.0: 3 ports detected [ 1.924150] ohci_hcd 0000:00:13.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18 [ 1.931468] ohci_hcd 0000:00:13.0: OHCI Host Controller [ 1.936798] ohci_hcd 0000:00:13.0: new USB bus registered, assigned bus number 5 [ 1.944410] ohci_hcd 0000:00:13.0: irq 18, io mem 0xd8406000 [ 2.008164] hub 5-0:1.0: USB hub found [ 2.012096] hub 5-0:1.0: 3 ports detected [ 2.016308] ohci_hcd 0000:00:13.1: PCI INT A -> GSI 18 (level, low) -> IRQ 18 [ 2.023615] ohci_hcd 0000:00:13.1: OHCI Host Controller [ 2.029051] ohci_hcd 0000:00:13.1: new USB bus registered, assigned bus number 6 [ 2.036810] ohci_hcd 0000:00:13.1: irq 18, io mem 0xd8407000 [ 2.100076] hub 6-0:1.0: USB hub found [ 2.103886] hub 6-0:1.0: 3 ports detected [ 2.108100] ohci_hcd 0000:00:14.5: PCI INT C -> GSI 18 (level, low) -> IRQ 18 [ 2.115384] ohci_hcd 0000:00:14.5: OHCI Host Controller [ 2.120715] ohci_hcd 0000:00:14.5: new USB bus registered, assigned bus number 7 [ 2.132071] ohci_hcd 0000:00:14.5: irq 18, io mem 0xd8408000 [ 2.196177] hub 7-0:1.0: USB hub found [ 2.200101] hub 7-0:1.0: 2 ports detected [ 2.204306] uhci_hcd: USB Universal Host Controller Interface driver [ 2.210948] i8042: PNP: No PS/2 controller found. Probing ports directly. [ 2.218340] serio: i8042 KBD port at 0x60,0x64 irq 1 [ 2.223674] serio: i8042 AUX port at 0x60,0x64 irq 12 [ 2.229041] mousedev: PS/2 mouse device common for all mice [ 2.235052] rtc_cmos 00:01: RTC can wake from S4 [ 2.240023] rtc_cmos 00:01: rtc core: registered rtc_cmos as rtc0 [ 2.246323] rtc0: alarms up to one day, 114 bytes nvram, hpet irqs [ 2.252648] device-mapper: uevent: version 1.0.3 [ 2.257447] device-mapper: ioctl: 4.19.1-ioctl (2011-01-07) initialised: dm-devel@redhat.com [ 2.266156] device-mapper: multipath: version 1.2.0 loaded [ 2.267928] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input2 [ 2.280470] device-mapper: multipath round-robin: version 1.0.0 loaded [ 2.287144] EISA: Probing bus 0 at eisa.0 [ 2.291296] EISA: Cannot allocate resource for mainboard [ 2.296732] Cannot allocate resource for EISA slot 1 [ 2.301783] Cannot allocate resource for EISA slot 2 [ 2.306883] Cannot allocate resource for EISA slot 3 [ 2.311986] Cannot allocate resource for EISA slot 4 [ 2.317104] Cannot allocate resource for EISA slot 5 [ 2.322191] Cannot allocate resource for EISA slot 6 [ 2.327296] Cannot allocate resource for EISA slot 7 [ 2.332407] Cannot allocate resource for EISA slot 8 [ 2.337460] EISA: Detected 0 cards. [ 2.341224] cpuidle: using governor ladder [ 2.345457] cpuidle: using governor menu [ 2.349696] TCP cubic registered [ 2.353093] NET: Registered protocol family 10 [ 2.358068] NET: Registered protocol family 17 [ 2.362653] Registering the dns_resolver key type [ 2.364046] usb 4-3: new full speed USB device using ohci_hcd and address 2 [ 2.374578] powernow-k8: Found 1 AMD Athlon(tm) II X2 250 Processor (2 cpu cores) (version 2.20.00) [ 2.383791] powernow-k8: 0 : pstate 0 (3000 MHz) [ 2.388831] powernow-k8: 1 : pstate 1 (2300 MHz) [ 2.393841] powernow-k8: 2 : pstate 2 (1800 MHz) [ 2.398849] powernow-k8: 3 : pstate 3 (800 MHz) [ 2.403824] Using IPI No-Shortcut mode [ 2.407850] PM: Hibernation image not present or could not be loaded. [ 2.407865] registered taskstats version 1 [ 2.412545] Magic number: 3:174:162 [ 2.416560] rtc_cmos 00:01: setting system clock to 2011-11-28 04:11:55 UTC (1322453515) [ 2.424784] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found [ 2.430930] EDD information not available. [ 2.435261] Freeing unused kernel memory: 700k freed [ 2.440730] Write protecting the kernel text: 5192k [ 2.445965] Write protecting the kernel read-only data: 2068k [ 2.480242] ramzswap: disk size not provided. You can use disksize_kb module param to specify size. [ 2.480246] Using default: (25% of RAM). [ 2.493428] ramzswap: disk size set to 450412 kB [ 2.503124] <30>udev[72]: starting version 167 [ 2.547042] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded [ 2.554429] ahci 0000:00:11.0: version 3.0 [ 2.554453] ahci 0000:00:11.0: PCI INT A -> GSI 22 (level, low) -> IRQ 22 [ 2.563151] ahci 0000:00:11.0: irq 41 for MSI/MSI-X [ 2.563257] ahci 0000:00:11.0: AHCI 0001.0100 32 slots 4 ports 3 Gbps 0xf impl SATA mode [ 2.571480] ahci 0000:00:11.0: flags: 64bit ncq sntf ilck pm led clo pmp pio slum part ccc [ 2.580907] r8169 0000:02:00.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18 [ 2.587899] scsi0 : ahci [ 2.590696] r8169 0000:02:00.0: setting latency timer to 64 [ 2.590779] r8169 0000:02:00.0: irq 42 for MSI/MSI-X [ 2.591123] r8169 0000:02:00.0: eth0: RTL8168d/8111d at 0xf8006000, ed:0b:00:00:e0:00, XID 083000c0 IRQ 42 [ 2.600931] scsi1 : ahci [ 2.616971] scsi2 : ahci [ 2.622872] scsi3 : ahci [ 2.625879] ata1: SATA max UDMA/133 abar m1024@0xd8409000 port 0xd8409100 irq 41 [ 2.633457] ata2: SATA max UDMA/133 abar m1024@0xd8409000 port 0xd8409180 irq 41 [ 2.640928] ata3: SATA max UDMA/133 abar m1024@0xd8409000 port 0xd8409200 irq 41 [ 2.648461] ata4: SATA max UDMA/133 abar m1024@0xd8409000 port 0xd8409280 irq 41 [ 2.659527] scsi4 : pata_atiixp [ 2.663609] scsi5 : pata_atiixp [ 2.667554] ata5: PATA max UDMA/100 cmd 0x1f0 ctl 0x3f6 bmdma 0x3010 irq 14 [ 2.674942] ata6: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0x3018 irq 15 [ 2.682108] usb 3-1: new low speed USB device using ohci_hcd and address 2 [ 2.878180] input: HID 0ccd:0077 as /devices/pci0000:00/0000:00:12.1/usb4/4-3/4-3:1.3/input/input3 [ 2.887658] generic-usb 0003:0CCD:0077.0001: input,hidraw0: USB HID v1.00 Device [HID 0ccd:0077] on usb-0000:00:12.1-3/input3 [ 2.909466] input: HID 04d9:1203 as /devices/pci0000:00/0000:00:12.0/usb3/3-1/3-1:1.0/input/input4 [ 2.918653] generic-usb 0003:04D9:1203.0002: input,hidraw1: USB HID v1.11 Keyboard [HID 04d9:1203] on usb-0000:00:12.0-1/input0 [ 2.947205] input: HID 04d9:1203 as /devices/pci0000:00/0000:00:12.0/usb3/3-1/3-1:1.1/input/input5 [ 2.956468] generic-usb 0003:04D9:1203.0003: input,hidraw2: USB HID v1.11 Device [HID 04d9:1203] on usb-0000:00:12.0-1/input1 [ 2.968128] usbcore: registered new interface driver usbhid [ 2.973907] usbhid: USB HID core driver [ 2.980069] ata3: SATA link down (SStatus 0 SControl 300) [ 2.985612] ata2: SATA link down (SStatus 0 SControl 300) [ 2.996029] usb 3-2: new low speed USB device using ohci_hcd and address 3 [ 3.006161] ata4: SATA link down (SStatus 0 SControl 300) [ 3.160050] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300) [ 3.167349] ata1.00: ATA-8: Hitachi HDP725050GLA360, GM4OA52A, max UDMA/133 [ 3.174467] ata1.00: 976773168 sectors, multi 0: LBA48 NCQ (depth 31/32), AA [ 3.181438] input: B16_b_02 USB-PS/2 Optical Mouse as /devices/pci0000:00/0000:00:12.0/usb3/3-2/3-2:1.0/input/input6 [ 3.181527] generic-usb 0003:046D:C024.0004: input,hidraw3: USB HID v1.10 Mouse [B16_b_02 USB-PS/2 Optical Mouse] on usb-0000:00:12.0-2/input0 [ 3.206421] ata1.00: configured for UDMA/133 [ 3.211028] scsi 0:0:0:0: Direct-Access ATA Hitachi HDP72505 GM4O PQ: 0 ANSI: 5 [ 3.219437] sd 0:0:0:0: Attached scsi generic sg0 type 0 [ 3.224942] sd 0:0:0:0: [sda] 976773168 512-byte logical blocks: (500 GB/465 GiB) [ 3.232665] sd 0:0:0:0: [sda] Write Protect is off [ 3.237575] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 3.237607] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 3.259506] sda: sda1 sda2 sda3 [ 3.263262] sd 0:0:0:0: [sda] Attached SCSI disk [ 3.726054] Btrfs loaded [ 3.737570] xor: automatically using best checksumming function: pIII_sse [ 3.764019] pIII_sse : 3201.000 MB/sec [ 3.768509] xor: using function: pIII_sse (3201.000 MB/sec) [ 3.780889] device-mapper: dm-raid45: initialized v0.2594b [ 3.789674] md: linear personality registered for level -1 [ 3.801132] md: multipath personality registered for level -4 [ 3.810274] md: raid0 personality registered for level 0 [ 3.824589] md: raid1 personality registered for level 1 [ 3.832942] async_tx: api initialized (async) [ 3.904032] raid6: int32x1 1345 MB/s [ 3.972021] raid6: int32x2 1402 MB/s [ 4.040070] raid6: int32x4 1043 MB/s [ 4.108014] raid6: int32x8 803 MB/s [ 4.176023] raid6: mmxx1 2483 MB/s [ 4.244015] raid6: mmxx2 4697 MB/s [ 4.312034] raid6: sse1x1 2176 MB/s [ 4.380035] raid6: sse1x2 3592 MB/s [ 4.448024] raid6: sse2x1 4149 MB/s [ 4.520032] raid6: sse2x2 6885 MB/s [ 4.523959] raid6: using algorithm sse2x2 (6885 MB/s) [ 4.545270] md: raid6 personality registered for level 6 [ 4.551624] md: raid5 personality registered for level 5 [ 4.557329] md: raid4 personality registered for level 4 [ 4.572376] md: raid10 personality registered for level 10 [ 16.346420] EXT3-fs (dm-0): recovery required on readonly filesystem [ 16.353258] EXT3-fs (dm-0): write access will be enabled during recovery [ 16.382409] EXT3-fs: barriers not enabled [ 17.920337] kjournald starting. Commit interval 5 seconds [ 17.920476] EXT3-fs (dm-0): orphan cleanup on readonly fs [ 17.920482] ext3_orphan_cleanup: deleting unreferenced inode 26924626 [ 17.920511] EXT3-fs (dm-0): 1 orphan inode deleted [ 17.920512] EXT3-fs (dm-0): recovery complete [ 17.950387] EXT3-fs (dm-0): mounted filesystem with ordered data mode [ 41.807682] <30>udev[423]: starting version 167 [ 41.827903] lp: driver loaded but no devices found [ 41.885666] shpchp 0000:00:01.0: HPC vendor_id 1022 device_id 9602 ss_vid 1022 ss_did 9602 [ 41.885670] shpchp 0000:00:01.0: Cannot reserve MMIO region [ 41.893246] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4 [ 42.028134] ACPI: resource piix4_smbus [io 0x0b00-0x0b07] conflicts with ACPI region SMB0 [io 0xb00-0xb0b] [ 42.028137] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver [ 42.064040] SP5100 TCO timer: SP5100 TCO WatchDog Timer Driver v0.01 [ 42.072226] SP5100 TCO timer: mmio address 0xfec000f0 already in use [ 42.092417] <30>udev[513]: renamed network interface eth0 to eth5 [ 42.187984] type=1400 audit(1322453555.264:2): apparmor="STATUS" operation="profile_load" name="/sbin/dhclient" pid=716 comm="apparmor_parser" [ 42.188312] type=1400 audit(1322453555.268:3): apparmor="STATUS" operation="profile_load" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=716 comm="apparmor_parser" [ 42.188483] type=1400 audit(1322453555.268:4): apparmor="STATUS" operation="profile_load" name="/usr/lib/connman/scripts/dhclient-script" pid=716 comm="apparmor_parser" [ 42.189192] type=1400 audit(1322453555.268:5): apparmor="STATUS" operation="profile_replace" name="/sbin/dhclient" pid=683 comm="apparmor_parser" [ 42.189842] type=1400 audit(1322453555.268:6): apparmor="STATUS" operation="profile_replace" name="/usr/lib/NetworkManager/nm-dhcp- client.action" pid=683 comm="apparmor_parser" [ 42.190262] type=1400 audit(1322453555.268:7): apparmor="STATUS" operation="profile_replace" name="/usr/lib/connman/scripts/dhclient-script" pid=683 comm="apparmor_parser" [ 42.195769] cfg80211: Calling CRDA to update world regulatory domain [ 42.293006] cfg80211: World regulatory domain updated: [ 42.293009] cfg80211: (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp) [ 42.293011] cfg80211: (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) [ 42.293013] cfg80211: (2457000 KHz - 2482000 KHz @ 20000 KHz), (300 mBi, 2000 mBm) [ 42.293015] cfg80211: (2474000 KHz - 2494000 KHz @ 20000 KHz), (300 mBi, 2000 mBm) [ 42.293017] cfg80211: (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) [ 42.293019] cfg80211: (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) [ 42.385685] ath9k 0000:03:06.0: PCI INT A -> GSI 21 (level, low) -> IRQ 21 [ 42.552877] usbcore: registered new interface driver snd-usb-audio [ 43.959786] ath: EEPROM regdomain: 0x30 [ 43.959788] ath: EEPROM indicates we should expect a direct regpair map [ 43.959790] ath: Country alpha2 being used: AM [ 43.959792] ath: Regpair used: 0x30 [ 43.959906] cfg80211: Updating information on frequency 2412 MHz for a 20 MHz width channel with regulatory rule: [ 43.959908] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959910] cfg80211: Updating information on frequency 2417 MHz for a 20 MHz width channel with regulatory rule: [ 43.959912] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959914] cfg80211: Updating information on frequency 2422 MHz for a 20 MHz width channel with regulatory rule: [ 43.959916] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959917] cfg80211: Updating information on frequency 2427 MHz for a 20 MHz width channel with regulatory rule: [ 43.959919] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959921] cfg80211: Updating information on frequency 2432 MHz for a 20 MHz width channel with regulatory rule: [ 43.959923] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959924] cfg80211: Updating information on frequency 2437 MHz for a 20 MHz width channel with regulatory rule: [ 43.959926] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959928] cfg80211: Updating information on frequency 2442 MHz for a 20 MHz width channel with regulatory rule: [ 43.959930] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959931] cfg80211: Updating information on frequency 2447 MHz for a 20 MHz width channel with regulatory rule: [ 43.959933] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959935] cfg80211: Updating information on frequency 2452 MHz for a 20 MHz width channel with regulatory rule: [ 43.959937] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959938] cfg80211: Updating information on frequency 2457 MHz for a 20 MHz width channel with regulatory rule: [ 43.959940] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959942] cfg80211: Updating information on frequency 2462 MHz for a 20 MHz width channel with regulatory rule: [ 43.959943] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.959945] cfg80211: Disabling freq 2467 MHz as custom regd has no rule that fits a 20 MHz wide channel [ 43.959947] cfg80211: Disabling freq 2472 MHz as custom regd has no rule that fits a 20 MHz wide channel [ 43.959949] cfg80211: Disabling freq 2484 MHz as custom regd has no rule that fits a 20 MHz wide channel [ 43.962455] cfg80211: Updating information on frequency 2412 MHz for a 20 MHz width channel with regulatory rule: [ 43.962457] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962459] cfg80211: Updating information on frequency 2417 MHz for a 20 MHz width channel with regulatory rule: [ 43.962461] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962463] cfg80211: Updating information on frequency 2422 MHz for a 20 MHz width channel with regulatory rule: [ 43.962465] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962467] cfg80211: Updating information on frequency 2427 MHz for a 20 MHz width channel with regulatory rule: [ 43.962469] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962470] cfg80211: Updating information on frequency 2432 MHz for a 20 MHz width channel with regulatory rule: [ 43.962472] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962474] cfg80211: Updating information on frequency 2437 MHz for a 20 MHz width channel with regulatory rule: [ 43.962476] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962478] cfg80211: Updating information on frequency 2442 MHz for a 20 MHz width channel with regulatory rule: [ 43.962480] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962482] cfg80211: Updating information on frequency 2447 MHz for a 20 MHz width channel with regulatory rule: [ 43.962484] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962485] cfg80211: Updating information on frequency 2452 MHz for a 20 MHz width channel with regulatory rule: [ 43.962487] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962489] cfg80211: Updating information on frequency 2457 MHz for a 20 MHz width channel with regulatory rule: [ 43.962491] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962493] cfg80211: Updating information on frequency 2462 MHz for a 20 MHz width channel with regulatory rule: [ 43.962495] cfg80211: 2402000 KHz - 2472000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962497] cfg80211: Updating information on frequency 2467 MHz for a 20 MHz width channel with regulatory rule: [ 43.962499] cfg80211: 2457000 KHz - 2482000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962500] cfg80211: Updating information on frequency 2472 MHz for a 20 MHz width channel with regulatory rule: [ 43.962502] cfg80211: 2457000 KHz - 2482000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.962504] cfg80211: Updating information on frequency 2484 MHz for a 20 MHz width channel with regulatory rule: [ 43.962506] cfg80211: 2474000 KHz - 2494000 KHz @ KHz), (300 mBi, 2000 mBm) [ 43.970787] ieee80211 phy0: Selected rate control algorithm 'ath9k_rate_control' [ 43.971254] Registered led device: ath9k-phy0::radio [ 43.971268] Registered led device: ath9k-phy0::assoc [ 43.971281] Registered led device: ath9k-phy0::tx [ 43.971296] Registered led device: ath9k-phy0::rx [ 43.971299] ieee80211 phy0: Atheros AR9280 Rev:2 mem=0xf8440000, irq=21 [ 43.971422] cfg80211: Calling CRDA for country: AM [ 43.985168] cfg80211: Updating information on frequency 2412 MHz for a 20 MHz width channel with regulatory rule: [ 43.985171] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985173] cfg80211: Updating information on frequency 2417 MHz for a 20 MHz width channel with regulatory rule: [ 43.985176] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985177] cfg80211: Updating information on frequency 2422 MHz for a 20 MHz width channel with regulatory rule: [ 43.985179] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985181] cfg80211: Updating information on frequency 2427 MHz for a 20 MHz width channel with regulatory rule: [ 43.985183] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985184] cfg80211: Updating information on frequency 2432 MHz for a 20 MHz width channel with regulatory rule: [ 43.985186] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985188] cfg80211: Updating information on frequency 2437 MHz for a 20 MHz width channel with regulatory rule: [ 43.985189] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985191] cfg80211: Updating information on frequency 2442 MHz for a 20 MHz width channel with regulatory rule: [ 43.985193] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985194] cfg80211: Updating information on frequency 2447 MHz for a 20 MHz width channel with regulatory rule: [ 43.985196] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985198] cfg80211: Updating information on frequency 2452 MHz for a 20 MHz width channel with regulatory rule: [ 43.985200] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985201] cfg80211: Updating information on frequency 2457 MHz for a 20 MHz width channel with regulatory rule: [ 43.985203] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985205] cfg80211: Updating information on frequency 2462 MHz for a 20 MHz width channel with regulatory rule: [ 43.985207] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985208] cfg80211: Updating information on frequency 2467 MHz for a 20 MHz width channel with regulatory rule: [ 43.985210] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985212] cfg80211: Updating information on frequency 2472 MHz for a 20 MHz width channel with regulatory rule: [ 43.985214] cfg80211: 2402000 KHz - 2482000 KHz @ KHz), (N/A mBi, 2000 mBm) [ 43.985215] cfg80211: Disabling freq 2484 MHz [ 43.985218] cfg80211: Regulatory domain changed to country: AM [ 43.985219] cfg80211: (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp) [ 43.985221] cfg80211: (2402000 KHz - 2482000 KHz @ 40000 KHz), (N/A, 2000 mBm) [ 43.985222] cfg80211: (5170000 KHz - 5250000 KHz @ 20000 KHz), (N/A, 1800 mBm) [ 43.985224] cfg80211: (5250000 KHz - 5330000 KHz @ 20000 KHz), (N/A, 1800 mBm) [ 44.068231] ADDRCONF(NETDEV_UP): wlan0: link is not ready [ 44.213372] EXT3-fs (dm-0): using internal journal [ 44.721119] EXT3-fs: barriers not enabled [ 44.721749] kjournald starting. Commit interval 5 seconds [ 44.775506] EXT3-fs (sda2): using internal journal [ 44.775515] EXT3-fs (sda2): mounted filesystem with ordered data mode [ 44.824766] RPC: Registered udp transport module. [ 44.824769] RPC: Registered tcp transport module. [ 44.824770] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 44.834537] FS-Cache: Loaded [ 44.863058] FS-Cache: Netfs 'nfs' registered for caching [ 44.906194] Installing knfsd (copyright (C) 1996 okir@monad.swb.de). [ 44.963589] type=1400 audit(1322453558.040:8): apparmor="STATUS" operation="profile_replace" name="/sbin/dhclient" pid=1047 comm="apparmor_parser" [ 44.963867] type=1400 audit(1322453558.040:9): apparmor="STATUS" operation="profile_replace" name="/usr/lib/NetworkManager/nm-dhcp- client.action" pid=1047 comm="apparmor_parser" [ 44.964245] type=1400 audit(1322453558.044:10): apparmor="STATUS" operation="profile_replace" name="/usr/lib/connman/scripts/dhclient-script" pid=1047 comm="apparmor_parser" [ 44.972367] type=1400 audit(1322453558.052:11): apparmor="STATUS" operation="profile_load" name="/usr/bin/evince" pid=1049 comm="apparmor_parser" [ 45.078531] wlan0: authenticate with 00:24:01:63:89:bd (try 1) [ 45.080800] wlan0: authenticated [ 45.080823] wlan0: associate with 00:24:01:63:89:bd (try 1) [ 45.083291] wlan0: RX AssocResp from 00:24:01:63:89:bd (capab=0x401 status=0 aid=2) [ 45.083294] wlan0: associated [ 45.083608] ADDRCONF(NETDEV_CHANGE): wlan0: link becomes ready [ 45.097598] ppdev: user-space parallel port driver [ 45.582849] kvm: Nested Virtualization enabled [ 45.809676] pci 0000:01:05.0: PCI INT A -> GSI 18 (level, low) -> IRQ 18 [ 45.834999] [drm] Initialized drm 1.1.0 20060810 [ 45.864594] [drm] radeon defaulting to kernel modesetting. [ 45.864597] [drm] radeon kernel modesetting enabled. [ 45.864657] radeon 0000:01:05.0: setting latency timer to 64 [ 45.867133] [drm] initializing kernel modesetting (RS880 0x1002:0x9710). [ 45.867160] [drm] register mmio base: 0xD8100000 [ 45.867162] [drm] register mmio size: 65536 [ 45.867239] ATOM BIOS: B43106 [ 45.867270] radeon 0000:01:05.0: VRAM: 256M 0x00000000C0000000 - 0x00000000CFFFFFFF (256M used) [ 45.867272] radeon 0000:01:05.0: GTT: 512M 0x00000000A0000000 - 0x00000000BFFFFFFF [ 45.867628] [drm] Detected VRAM RAM=256M, BAR=256M [ 45.867631] [drm] RAM width 32bits DDR [ 45.875994] [TTM] Zone kernel: Available graphics memory: 438016 kiB. [ 45.875996] [TTM] Zone highmem: Available graphics memory: 900832 kiB. [ 45.876015] [TTM] Initializing pool allocator. [ 45.876088] [drm] radeon: 256M of VRAM memory ready [ 45.876089] [drm] radeon: 512M of GTT memory ready. [ 45.876105] [drm] Supports vblank timestamp caching Rev 1 (10.10.2010). [ 45.876106] [drm] Driver supports precise vblank timestamp query. [ 45.876140] [drm] radeon: irq initialized. [ 45.876142] [drm] GART: num cpu pages 131072, num gpu pages 131072 [ 45.876988] [drm] Loading RS780 Microcode [ 45.876990] radeon_cp.0: Missing Free firmware [ 45.915550] [drm:r600_startup] *ERROR* Failed to load firmware! [ 45.921989] radeon 0000:01:05.0: disabling GPU acceleration [ 45.928744] radeon 0000:01:05.0: ef428800 unpin not necessary [ 45.928750] radeon 0000:01:05.0: ef428800 unpin not necessary [ 45.928757] [drm] Enabling audio support [ 45.928766] failed to evaluate ATIF got AE_BAD_PARAMETER [ 45.929090] [drm] Radeon Display Connectors [ 45.929094] [drm] Connector 0: [ 45.929097] [drm] VGA [ 45.929101] [drm] DDC: 0x7e40 0x7e40 0x7e44 0x7e44 0x7e48 0x7e48 0x7e4c 0x7e4c [ 45.929104] [drm] Encoders: [ 45.929107] [drm] CRT1: INTERNAL_KLDSCP_DAC1 [ 45.929110] [drm] Connector 1: [ 45.929112] [drm] HDMI-A [ 45.929114] [drm] HPD3 [ 45.929118] [drm] DDC: 0x7e50 0x7e50 0x7e54 0x7e54 0x7e58 0x7e58 0x7e5c 0x7e5c [ 45.929121] [drm] Encoders: [ 45.929124] [drm] DFP3: INTERNAL_KLDSCP_LVTMA [ 45.993047] [drm] radeon: power management initialized [ 46.117232] [drm] fb mappable at 0xC0040000 [ 46.117237] [drm] vram apper at 0xC0000000 [ 46.117240] [drm] size 5324800 [ 46.117243] [drm] fb depth is 24 [ 46.117246] [drm] pitch is 5888 [ 46.119045] fbcon: radeondrmfb (fb0) is primary device [ 46.122246] Console: switching to colour frame buffer device 180x56 [ 46.122257] fb0: radeondrmfb frame buffer device [ 46.122261] drm: registered panic notifier [ 46.122271] [drm] Initialized radeon 2.8.0 20080528 for 0000:01:05.0 on minor 0 [ 55.584060] wlan0: no IPv6 routers present
This dmesg was made after booting from coreboot which contained the following commits: 2687844 M4A785T-M: fix ACPI's P-States Table 1eb55d0 Add ASUS M4A785T-M mainboard support e8d0122 RS780: print the vgainfo 0dbfb54 Remove unused code files and cosmetic changes (HEAD from master)
Denis.
-
Denis 'GNUtoo' Carikli -
Denis Carikli -
Paul Menzel