Hello,
as i saw ASUS M2N-E motherboard on the list of supported motherboards, I decided to give a try to this very interesting project. I compiled coreboot via crossgcc with very default options, I only choose the vendor, the board and SeaBIOS as payload.
Everything went fine and I flashed coreboot.rom via flashrom utility. Also here everything went fine.
Then I did restart, but there was no VGA output. So I connected my laptop as serial console and got an output.
According to this output coreboot starts, initializes some of the hardware but in some moment does softreset and this is happening in the infinite loop.
I saved the output which looks like this:
coreboot-4.0-2082-gccf28ba Tue Mar 6 14:42:21 CET 2012 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=0x00 Enabling routing table for node 00 done. Enabling UP settings coherent_ht_finalize done core0 started: started ap apicid: * AP 01started
SBLink=00 NC node|link=00 entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x807f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x0, freq=0x6, needs_reset=0x1 dev2 old_freq=0x0, freq=0x6, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x1 after optimize_link_read_pointers_chain, reset_needed=0x1 mcp55_num:01 ht reset -
coreboot-4.0-2082-gccf28ba Tue Mar 6 14:42:21 CET 2012 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=0x00 Enabling routing table for node 00 done. Enabling UP settings coherent_ht_finalize done core0 started: started ap apicid: * AP 01started
SBLink=00 NC node|link=00 entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x7f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 mcp55_num:01 Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000cef10 Enable 64MuxMode & BurstLength32 Unbuffered 266MHz 266MHz set_ecc spd_device: 0x53 Interleaving disabled RAM end at 0x00080000 kB Ram3 ECC enabled Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 512MB, type WB set DQS timing:RcvrEn:Pass1: 00 CTLRMaxDelay=06 done set DQS timing:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce9d0 TrainDQSPos: MutualCSPassW[48] :000ce8b8 TrainDQSPos: MutualCSPassW[48] :000ce8b8 TrainDQSPos: MutualCSPassW[48] :000ce8b8 TrainDQSPos: MutualCSPassW[48] :000ce8b8 done set DQS timing:RcvrEn:Pass2: 00 CTLRMaxDelay=5a done Total DQS Training : tsc [00]=00000000151d874b Total DQS Training : tsc [01]=00000000159134eb Total DQS Training : tsc [02]=0000000019f3270b Total DQS Training : tsc [03]=000000001a93b1df Ram4 v_esp=000cef58 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... DoneM ˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙
INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} ---
Issuing SOFT_RESET...
coreboot-4.0-2082-gccf28ba Tue Mar 6 14:42:21 CET 2012 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=0x00 Enabling routing table for node 00 done. Enabling UP settings coherent_ht_finalize done core0 started: started ap apicid: * AP 01started
SBLink=00 NC node|link=00 entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x7f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 mcp55_num:01 Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000cef10 Enable 64MuxMode & BurstLength32 Unbuffered 266MHz 266MHz set_ecc spd_device: 0x53 Interleaving disabled RAM end at 0x00080000 kB Ram3 ECC enabled Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 512MB, type WB set DQS timing:RcvrEn:Pass1: 00 CTLRMaxDelay=06 done set DQS timing:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce9d0 TrainDQSPos: MutualCSPassW[48] :000ce8b8 TrainDQSPos: MutualCSPassW[48] :000ce8b8 TrainDQSPos: MutualCSPassW[48] :000ce8b8 TrainDQSPos: MutualCSPassW[48] :000ce8b8 done set DQS timing:RcvrEn:Pass2: 00 CTLRMaxDelay=5a done Total DQS Training : tsc [00]=00000000151e5153 Total DQS Training : tsc [01]=00000000159202d7 Total DQS Training : tsc [02]=0000000019f3b027 Total DQS Training : tsc [03]=000000001a941b7b Ram4 v_esp=000cef58 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack...
INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} ---
Issuing SOFT_RESET...
coreboot-4.0-2082-gccf28ba Tue Mar 6 14:42:21 CET 2012 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=0x00 Enabling routing table for node 00 done. Enabling UP settings coherent_ht_finalize done core0 started: started ap apicid: * AP 01started
SBLink=00 NC node|link=00 entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x7f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 mcp55_num:01 Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000cef10 Enable 64MuxMode & BurstLength32 Unbuffered 266MHz 266MHz set_ecc spd_device: 0x53 Interleaving disabled RAM end at 0x00080000 kB Ram3 ECC enabled Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 512MB, type WB set DQS timing:RcvrEn:Pass1: 00 CTLRMaxDelay=06 done set DQS timing:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce9d0 TrainDQSPos: MutualCSPassW[48] :000ce8b8 TrainDQSPos: MutualCSPassW[48] :000ce8b8 TrainDQSPos: MutualCSPassW[48] :000ce8b8 TrainDQSPos: MutualCSPassW[48] :000ce8b8 done set DQS timing:RcvrEn:Pass2: 00 CTLRMaxDelay=5a done Total DQS Training : tsc [00]=00000000151bd15f Total DQS Training : tsc [01]=00000000158f7f1f Total DQS Training : tsc [02]=0000000019f16f1f Total DQS Training : tsc [03]=000000001a91d8e7 Ram4 v_esp=000cef58 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... DneM ˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙ß˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙˙
INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} ---
Issuing SOFT_RESET...
coreboot-4.0-2082-gccf28ba Tue Mar 6 14:42:21 CET 2012 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=0x00 Enabling routing table for node 00 done. Enabling UP settings coherent_ht_finalize done core0 started: started ap apicid: * AP 01started
SBLink=00 NC node|link=00 entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x7f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 mcp55_num:01 Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000cef10 Enable 64MuxMode & BurstLength32 Unbuffered 266MHz 266MHz set_ecc spd_device: 0x53 Interleaving disabled RAM end at 0x00080000 kB Ram3 ECC enabled Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 512MB, type WB set DQS timing:RcvrEn:Pass1: 00 CTLRMaxDelay=06 done set DQS timing:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce9d0 TrainDQSPos: MutualCSPassW[48] :000ce8b8 TrainDQSPos: MutualCSPassW[48] :000ce8b8 TrainDQSPos: MutualCSPassW[48] :000ce8b8 TrainDQSPos: MutualCSPassW[48] :000ce8b8 done set DQS timing:RcvrEn:Pass2: 00 CTLRMaxDelay=5a done Total DQS Training : tsc [00]=00000000151f1cff Total DQS Training : tsc [01]=000000001592ca9f Total DQS Training : tsc [02]=0000000019f5cac3 Total DQS Training : tsc [03]=000000001a969e5b Ram4 v_esp=000cef58 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Ene t
INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} ---
Issuing SOFT_RESET...
coreboot-4.0-2082-gccf28ba Tue Mar 6 14:42:21 CET 2012 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=0x00 Enabling routing table for node 00 done. Enabling UP settings coherent_ht_finalize done core0 started: started ap apicid: * AP 01started
SBLink=00 NC node|link=00 entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x7f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 mcp55_num:01 Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000cef10 Enable 64MuxMode & BurstLength32 Unbuffered 266MHz 266MHz set_ecc spd_device: 0x53 Interleaving disabled RAM end at 0x00080000 kB Ram3 ECC enabled Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 512MB, type WB set DQS timing:RcvrEn:Pass1: 00 CTLRMaxDelay=06 done set DQS timing:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce9d0 TrainDQSPos: MutualCSPassW[48] :000ce8b8 TrainDQSPos: MutualCSPassW[48] :000ce8b8 TrainDQSPos: MutualCSPassW[48] :000ce8b8 TrainDQSPos: MutualCSPassW[48] :000ce8b8 done set DQS timing:RcvrEn:Pass2: 00 CTLRMaxDelay=5a done Total DQS Training : tsc [00]=00000000151dc99f Total DQS Training : tsc [01]=0000000015917723 Total DQS Training : tsc [02]=0000000019f308b7 Total DQS Training : tsc [03]=000000001a936dab Ram4 v_esp=000cef58 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... DoDsabClearing initial memory region: Done Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (278528 bytes), entry @ 0x100000 Stage: done loading. Jumping to image.
INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} ---
Issuing SOFT_RESET...
....
Could anybody explain me what is wrong? I am not subscribed to the mailing list, so please use my email address as Cc. Thank you.
Pavel
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Pavel Hanák