[commit] r6221 - in trunk/src: include/cpu/amd mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/wyse/s50 northbridge/amd/gx2 southbridge/amd/cs5535
Author: myles Date: Wed Dec 29 22:12:10 2010 New Revision: 6221 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6221
Log: -Change the remaining GLIU1 port 5 register names from VIP (Video Input Port) to FG (FooGlue). As the GX2 has no VIP port. -Change the Memmory setup MSR register names so they correspond better to the databook. (Part1) This is less confusing for beginners. -Add a MSR printing function to northbridge.c like in the Geode LX code. -Remove the AES register names.(GX2 has no AES registers) -Delete some unused code. -Clean up GX2 northbridge code to match Geode LX code. -Add missing copyright header to northbridge.c. -Move hardcoded IRQ defining from northbridge.c to irq_tables.c .
Signed-off-by: Nils Jacobs njacobs8@hetnet.nl Acked-by: Myles Watson mylesgw@gmail.com
Modified: trunk/src/include/cpu/amd/gx2def.h trunk/src/mainboard/amd/rumba/irq_tables.c trunk/src/mainboard/lippert/frontrunner/irq_tables.c trunk/src/mainboard/wyse/s50/irq_tables.c trunk/src/mainboard/wyse/s50/mainboard.c trunk/src/northbridge/amd/gx2/northbridge.c trunk/src/northbridge/amd/gx2/northbridge.h trunk/src/northbridge/amd/gx2/northbridgeinit.c trunk/src/southbridge/amd/cs5535/cs5535.h
Modified: trunk/src/include/cpu/amd/gx2def.h ============================================================================== --- trunk/src/include/cpu/amd/gx2def.h Wed Dec 29 22:02:50 2010 (r6220) +++ trunk/src/include/cpu/amd/gx2def.h Wed Dec 29 22:12:10 2010 (r6221) @@ -77,8 +77,6 @@ #define GL1_GLCP 3 #define GL1_PCI 4 #define GL1_FG 5 -#define GL1_VIP 5 -#define GL1_AES 6
#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx - To get on GeodeLink one bit has to be set */ #define MSR_MC (GL0_MC << 29) /* 2000xxxx */ @@ -91,11 +89,6 @@ #define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 /* 4C00xxxx */ #define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 /* 5000xxxx */ #define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */ -#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */ -#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */ - -/* South Bridge */ -#define SB_PORT 2 /* port of the SouthBridge */
/* GeodeLink Interface Unit 0 (GLIU0) port0 */ #define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000) @@ -386,20 +379,10 @@
/* FooGlue GLIU1 port 5 */ #define FG_GLD_MSR_CAP (MSR_FG + 0x2000) +#define FG_GLD_MSR_CONFIG (MSR_FG + 0x2001) #define FG_GLD_MSR_PM (MSR_FG + 0x2004) - -/* VIP GLIU1 port 5 */ -#define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000) -#define VIP_GLD_MSR_CONFIG (MSR_VIP + 0x2001) -#define VIP_GLD_MSR_PM (MSR_VIP + 0x2004) -#define VIP_BIST (MSR_VIP + 0x2005) -#define VIP_GIO_MSR_SEL (MSR_VIP + 0x2010) - -/* AES GLIU1 port 6 */ -#define AES_GLD_MSR_CAP (MSR_AES + 0x2000) -#define AES_GLD_MSR_CONFIG (MSR_AES + 0x2001) -#define AES_GLD_MSR_PM (MSR_AES + 0x2004) -#define AES_CONTROL (MSR_AES + 0x2006) +#define FG_GIO_MSR_SEL (MSR_FG + 0x2010) +#define FG_BIST (MSR_FG + 0x2005)
/* from MC spec */ #define MIN_MOD_BANKS 1 @@ -429,22 +412,75 @@
#define MSR_GL0 (GL1_GLIU0 << 29)
-/* Set up desc addresses from 20 - 3f */ +/* Set up desc addresses from 20 - E8 */ /* This is chip specific! */ +//remove after MSRINIT is gone #define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM */ #define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM */ #define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */ #define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R */ -#define MSR_GLIU0_SMM (MSR_GLIU0 + 0x26) /* BMO */ -#define MSR_GLIU0_DMM (MSR_GLIU0 + 0x27) /* BMO */
#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM */ #define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM */ #define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC */ #define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R */ -#define MSR_GLIU1_SMM (MSR_GLIU1 + 0x23) /* BM */ -#define MSR_GLIU1_DMM (MSR_GLIU1 + 0x24) /* BM */ -#define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU */ + +#define GLIU0_P2D_BM_0 (MSR_GLIU0 + 0x20) /* BASE1 */ +#define GLIU0_P2D_BM_1 (MSR_GLIU0 + 0x21) /* BASE2 */ +#define GLIU0_P2D_BM_2 (MSR_GLIU0 + 0x22) +#define GLIU0_P2D_BM_3 (MSR_GLIU0 + 0x23) +#define GLIU0_P2D_BM_4 (MSR_GLIU0 + 0x24) +#define GLIU0_P2D_BM_5 (MSR_GLIU0 + 0x25) + +#define GLIU0_P2D_BMO_0 (MSR_GLIU0 + 0x26) /* SMM */ +#define GLIU0_P2D_BMO_1 (MSR_GLIU0 + 0x27) /* DMM */ + +#define GLIU0_P2D_R_0 (MSR_GLIU0 + 0x28) /* SYSMEM */ + +#define GLIU0_P2D_RO_0 (MSR_GLIU0 + 0x29) +#define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A) +#define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B) + +#define GLIU0_P2D_SC_0 (MSR_GLIU0 + 0x2C) /* SHADOW */ + +#define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0) +#define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1) +#define GLIU0_IOD_BM_2 (MSR_GLIU0 + 0xE2) + +#define GLIU0_IOD_SC_0 (MSR_GLIU0 + 0xE3) +#define GLIU0_IOD_SC_1 (MSR_GLIU0 + 0xE4) +#define GLIU0_IOD_SC_2 (MSR_GLIU0 + 0xE5) +#define GLIU0_IOD_SC_3 (MSR_GLIU0 + 0xE6) +#define GLIU0_IOD_SC_4 (MSR_GLIU0 + 0xE7) +#define GLIU0_IOD_SC_5 (MSR_GLIU0 + 0xE8) + +#define GLIU1_P2D_BM_0 (MSR_GLIU1 + 0x20) /* BASE1 */ +#define GLIU1_P2D_BM_1 (MSR_GLIU1 + 0x21) /* BASE2 */ +#define GLIU1_P2D_BM_2 (MSR_GLIU1 + 0x22) +#define GLIU1_P2D_BM_3 (MSR_GLIU1 + 0x23) /* SMM */ +#define GLIU1_P2D_BM_4 (MSR_GLIU1 + 0x24) /* DMM */ +#define GLIU1_P2D_BM_5 (MSR_GLIU1 + 0x25) +#define GLIU1_P2D_BM_6 (MSR_GLIU1 + 0x26) +#define GLIU1_P2D_BM_7 (MSR_GLIU1 + 0x27) +#define GLIU1_P2D_BM_8 (MSR_GLIU1 + 0x28) + +#define GLIU1_P2D_R_0 (MSR_GLIU1 + 0x29) /* SYSMEM */ +#define GLIU1_P2D_R_1 (MSR_GLIU1 + 0x2A) +#define GLIU1_P2D_R_2 (MSR_GLIU1 + 0x2B) +#define GLIU1_P2D_R_3 (MSR_GLIU1 + 0x2C) + +#define GLIU1_P2D_SC_0 (MSR_GLIU1 + 0x2D) /* SHADOW */ + +#define GLIU1_IOD_BM_0 (MSR_GLIU1 + 0xE0) +#define GLIU1_IOD_BM_1 (MSR_GLIU1 + 0xE1) +#define GLIU1_IOD_BM_2 (MSR_GLIU1 + 0xE2) + +#define GLIU1_IOD_SC_0 (MSR_GLIU1 + 0xE3) /* FooGlue F0 for FPU */ +#define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4) +#define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5) +#define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6) +#define GLIU1_IOD_SC_4 (MSR_GLIU1 + 0xE7) +#define GLIU1_IOD_SC_5 (MSR_GLIU1 + 0xE8)
/* definitions that are "once you are mostly up, start VSA" type things */ #define SMM_OFFSET 0x40400000
Modified: trunk/src/mainboard/amd/rumba/irq_tables.c ============================================================================== --- trunk/src/mainboard/amd/rumba/irq_tables.c Wed Dec 29 22:02:50 2010 (r6220) +++ trunk/src/mainboard/amd/rumba/irq_tables.c Wed Dec 29 22:12:10 2010 (r6221) @@ -7,6 +7,24 @@
#include <arch/pirq_routing.h>
+/* Platform IRQs */ +#define PIRQA 11 +#define PIRQB 5 +#define PIRQC 10 +#define PIRQD 10 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */
Modified: trunk/src/mainboard/lippert/frontrunner/irq_tables.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/irq_tables.c Wed Dec 29 22:02:50 2010 (r6220) +++ trunk/src/mainboard/lippert/frontrunner/irq_tables.c Wed Dec 29 22:12:10 2010 (r6221) @@ -7,6 +7,24 @@
#include <arch/pirq_routing.h>
+/* Platform IRQs */ +#define PIRQA 11 +#define PIRQB 5 +#define PIRQC 10 +#define PIRQD 10 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */
Modified: trunk/src/mainboard/wyse/s50/irq_tables.c ============================================================================== --- trunk/src/mainboard/wyse/s50/irq_tables.c Wed Dec 29 22:02:50 2010 (r6220) +++ trunk/src/mainboard/wyse/s50/irq_tables.c Wed Dec 29 22:12:10 2010 (r6221) @@ -20,6 +20,24 @@
#include <arch/pirq_routing.h>
+/* Platform IRQs */ +#define PIRQA 11 +#define PIRQB 5 +#define PIRQC 10 +#define PIRQD 10 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */
Modified: trunk/src/mainboard/wyse/s50/mainboard.c ============================================================================== --- trunk/src/mainboard/wyse/s50/mainboard.c Wed Dec 29 22:02:50 2010 (r6220) +++ trunk/src/mainboard/wyse/s50/mainboard.c Wed Dec 29 22:12:10 2010 (r6221) @@ -21,13 +21,21 @@
#include <console/console.h> #include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <arch/io.h> #include "chip.h"
+static void init(struct device *dev) +{ + printk(BIOS_DEBUG, "S50 ENTER %s\n", __func__); + printk(BIOS_DEBUG, "S50 EXIT %s\n", __func__); +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + struct chip_operations mainboard_ops = { CHIP_NAME("WYSE S50 Mainboard") + .enable_dev = enable_dev, };
Modified: trunk/src/northbridge/amd/gx2/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.c Wed Dec 29 22:02:50 2010 (r6220) +++ trunk/src/northbridge/amd/gx2/northbridge.c Wed Dec 29 22:12:10 2010 (r6221) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Nils Jacobs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <console/console.h> #include <arch/io.h> #include <stdint.h> @@ -9,14 +29,162 @@ #include <bitops.h> #include "chip.h" #include "northbridge.h" -#include <cpu/amd/gx2def.h> #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> #include <cpu/amd/vr.h> #include <cpu/cpu.h> #include "../../../southbridge/amd/cs5536/cs5536.h"
-#define NORTHBRIDGE_FILE "northbridge.c" +void print_conf(void); + +/* Print the platform configuration - do before PCI init or it will not + * work right. + */ +void print_conf(void) +{ +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR + int i; + unsigned long iol; + msr_t msr; + + int cpu_msr_defs[] = { CPU_IM_CONFIG, CPU_DM_CONFIG0, + CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, + CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM, + GLCP_DELAY_CONTROLS, GL_END + }; + + int gliu0_msr_defs[] = { GLIU0_P2D_BM_0, GLIU0_P2D_BM_1, + GLIU0_P2D_BM_2, GLIU0_P2D_BM_3, GLIU0_P2D_BM_4, + GLIU0_P2D_BM_5, GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, + GLIU0_P2D_R_0, GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, + GLIU0_P2D_RO_2, GLIU0_P2D_SC_0, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, + GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, + GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5, + GLIU0_GLD_MSR_COH, GL_END + }; + + int gliu1_msr_defs[] = { GLIU1_P2D_BM_0, GLIU1_P2D_BM_1, + GLIU1_P2D_BM_2, GLIU1_P2D_BM_3, GLIU1_P2D_BM_4, + GLIU1_P2D_BM_5, GLIU1_P2D_BM_6, GLIU1_P2D_BM_7, + GLIU1_P2D_BM_8, GLIU1_P2D_R_0, GLIU1_P2D_R_1, + GLIU1_P2D_R_2, GLIU1_P2D_R_3, GLIU1_P2D_SC_0, + GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0, + GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3, GLIU1_IOD_SC_4, + GLIU1_IOD_SC_5, GLIU1_GLD_MSR_COH, GL_END + }; + + int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, + CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END + }; + + int lbar_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, GL_END + }; + + int irq_msr[] = { MDD_IRQM_YLOW, MDD_IRQM_YHIGH, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, + MDD_IRQM_PRIM, GL_END + }; + + int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, + GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, + GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END + }; + + int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, + MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6, + MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END + }; + + printk(BIOS_DEBUG, "---------- CPU ------------\n"); + + for (i = 0; cpu_msr_defs[i] != GL_END; i++) { + msr = rdmsr(cpu_msr_defs[i]); + printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", + cpu_msr_defs[i], msr.hi, msr.lo); + } + + printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n"); + + for (i = 0; gliu0_msr_defs[i] != GL_END; i++) { + msr = rdmsr(gliu0_msr_defs[i]); + printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", + gliu0_msr_defs[i], msr.hi, msr.lo); + } + + printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n"); + + for (i = 0; gliu1_msr_defs[i] != GL_END; i++) { + msr = rdmsr(gliu1_msr_defs[i]); + printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", + gliu1_msr_defs[i], msr.hi, msr.lo); + } + + printk(BIOS_DEBUG, "---------- RCONF ------------\n"); + + for (i = 0; rconf_msr[i] != GL_END; i++) { + msr = rdmsr(rconf_msr[i]); + printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], + msr.hi, msr.lo); + } + + printk(BIOS_DEBUG, "---------- VARIA ------------\n"); + msr = rdmsr(ATA_SB_IDE_CFG); + printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", ATA_SB_IDE_CFG, msr.hi, + msr.lo); + + msr = rdmsr(MDD_LEG_IO); + printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_LEG_IO, msr.hi, + msr.lo); + + msr = rdmsr(MDD_PIN_OPT); + printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_PIN_OPT, msr.hi, + msr.lo); + + printk(BIOS_DEBUG, "---------- PCI ------------\n"); + + for (i = 0; pci_msr[i] != GL_END; i++) { + msr = rdmsr(pci_msr[i]); + printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], + msr.hi, msr.lo); + } + + printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n"); + + for (i = 0; dma_msr[i] != GL_END; i++) { + msr = rdmsr(dma_msr[i]); + printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], + msr.hi, msr.lo); + } + + printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n"); + + for (i = 0; irq_msr[i] != GL_END; i++) { + msr = rdmsr(irq_msr[i]); + printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", irq_msr[i], + msr.hi, msr.lo); + } + + printk(BIOS_DEBUG, "---------- DIVIL LBAR -----------\n"); + + for (i = 0; lbar_msr[i] != GL_END; i++) { + msr = rdmsr(lbar_msr[i]); + printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", lbar_msr[i], + msr.hi, msr.lo); + } + + iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE); + printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", + GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol); + iol = inl(GPIOL_EVENTS_ENABLE); + printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", + GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol); + iol = inl(GPIOL_INPUT_INVERT_ENABLE); + printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", + GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol); + iol = inl(GPIO_MAPPER_X); + printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X, + iol); +#endif /* CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR */ +}
/* todo: add a resource record. We don't do this here because this may be called when * very little of the platform is actually working. @@ -47,12 +215,6 @@ return sizem; }
-/* here is programming for the various MSRs. */ -#define IM_QWAIT 0x100000 - -#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */ -#define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */ - /* these are the 8-bit attributes for controlling RCONF registers */ #define CACHE_DISABLE (1<<0) #define WRITE_ALLOCATE (1<<1) @@ -65,51 +227,6 @@ #define RAM_PROPERTIES (0) #define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE) #define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE) -/* build initializer for P2D MSR */ -#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}} -#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}} - -struct msr_defaults -{ - int msr_no; - msr_t msr; -} msr_defaults [] = { - {0x1700, {.hi = 0, .lo = IM_QWAIT}}, - {0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, .lo = DMCF_SERIAL_LOAD_MISSES}}, - /* now for GLPCI routing */ - /* GLIU0 */ - P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80), - P2D_BM(0x10000021, 0x1, 0x0, 0x80000, 0xfffe0), - P2D_SC(0x1000002c, 0x1, 0x0, 0x0, 0xff03, 0xC0000), - /* GLIU1 */ - P2D_BM(0x40000020, 0x1, 0x0, 0x0, 0xfff80), - P2D_BM(0x40000021, 0x1, 0x0, 0x80000, 0xfffe0), - P2D_SC(0x4000002d, 0x1, 0x0, 0x0, 0xff03, 0xC0000), - {0} -}; - -/* note that dev is NOT used -- yet */ -static void irq_init_steering(struct device *dev, u16 irq_map) -{ - /* Set up IRQ steering */ - u32 pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; - - printk(BIOS_DEBUG, "%s(%p [%08X], %04X)\n", __func__, dev, pciAddr, irq_map); - - /* The IRQ steering values (in hex) are effectively dcba, where: - * <a> represents the IRQ for INTA, - * <b> represents the IRQ for INTB, - * <c> represents the IRQ for INTC, and - * <d> represents the IRQ for INTD. - * Thus, a value of irq_map = 0xAA5B translates to: - * INTA = IRQB (IRQ 11) - * INTB = IRQ5 (IRQ 5) - * INTC = IRQA (IRQ 10) - * INTD = IRQA (IRQ 10) - */ - outl(pciAddr & ~3, 0xCF8); - outl(irq_map, 0xCFC); -}
/* setup_gx2_cache * @@ -191,26 +308,25 @@
static void northbridge_init(device_t dev) { - struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; - printk(BIOS_DEBUG, "northbridge: %s()\n", __func__); + printk(BIOS_SPEW, ">> Entering northbridge: %s()\n", __func__);
enable_shadow(dev); - irq_init_steering(dev, nb->irqmap); }
-/* due to vsa interactions, we need not not touch the nb settings ... */ -/* this is a test -- we are not sure it will work -- but it ought to */ -static void set_resources(struct device *dev) +static void northbridge_set_resources(struct device *dev) { + uint8_t line; + struct bus *bus;
for(bus = dev->link_list; bus; bus = bus->next) { if (bus->children) { + printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n", + bus->secondary); assign_resources(bus); } }
-#if 0 /* set a default latency timer */ pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
@@ -220,18 +336,17 @@ }
/* zero the irq settings */ - u8 line = pci_read_config8(dev, PCI_INTERRUPT_PIN); + line = pci_read_config8(dev, PCI_INTERRUPT_PIN); if (line) { pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); } /* set the cache line size, so far 64 bytes is good for everyone */ pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2); -#endif }
static struct device_operations northbridge_operations = { .read_resources = pci_dev_read_resources, - .set_resources = set_resources, + .set_resources = northbridge_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .enable = 0, @@ -244,24 +359,64 @@ .device = PCI_DEVICE_ID_NS_GX2, };
-/* FIXME handle UMA correctly. */ -#define FRAMEBUFFERK 4096 +#if CONFIG_WRITE_HIGH_TABLES==1 +#include <cbmem.h> +#endif
static void pci_domain_set_resources(device_t dev) { + int idx; + u32 tomk; + device_t mc_dev; + + printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); + + mc_dev = dev->link_list->children; + if (mc_dev) { + tomk = get_systop() / 1024; + /* Report the memory regions + All memory up to systop except 0xa0000-0xbffff */ + idx = 10; + ram_resource(dev, idx++, 0, 640); + ram_resource(dev, idx++, 768, tomk - 768); /* Systop - 0xc0000 -> KB */ + +#if CONFIG_WRITE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; +#endif + } + assign_resources(dev->link_list); }
+static void pci_domain_enable(device_t dev) +{ + printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); + + /* do this here for now -- this chip really breaks our device model */ + northbridge_init_early(); + cpubug(); + chipsetinit(); + setup_gx2(); + print_conf(); + do_vsmbios(); + graphics_init(); + pci_set_method(dev); +} + static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, .enable_resources = NULL, - .init = NULL, .scan_bus = pci_domain_scan_bus, + .enable = pci_domain_enable, };
static void cpu_bus_init(device_t dev) { + printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__); + initialize_cpus(dev->link_list); }
@@ -277,42 +432,16 @@ .scan_bus = 0, };
-void chipsetInit (void); - -#if CONFIG_WRITE_HIGH_TABLES==1 -#include <cbmem.h> -#endif - static void enable_dev(struct device *dev) { - printk(BIOS_DEBUG, "gx2 north: enable_dev\n"); - void do_vsmbios(void); + printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n", + __func__, dev->path.type);
/* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { - u32 tomk; - printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n"); - /* cpubug MUST be called before setup_gx2(), so we force the issue here */ - northbridgeinit(); - cpubug(); - chipsetinit(); - setup_gx2(); - do_vsmbios(); - graphics_init(); + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) dev->ops = &pci_domain_ops; - pci_set_method(dev); - tomk = ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE; -#if CONFIG_WRITE_HIGH_TABLES==1 - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; -#endif - ram_resource(dev, 0, 0, tomk); - } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { - printk(BIOS_DEBUG, "DEVICE_PATH_APIC_CLUSTER\n"); + else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) dev->ops = &cpu_bus_ops; - } - printk(BIOS_DEBUG, "gx2 north: end enable_dev\n"); }
struct chip_operations northbridge_amd_gx2_ops = {
Modified: trunk/src/northbridge/amd/gx2/northbridge.h ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.h Wed Dec 29 22:02:50 2010 (r6220) +++ trunk/src/northbridge/amd/gx2/northbridge.h Wed Dec 29 22:12:10 2010 (r6221) @@ -1,14 +1,16 @@ #ifndef NORTHBRIDGE_AMD_GX2_H #define NORTHBRIDGE_AMD_GX2_H
-#if !defined(__ROMCC__) && !defined(ASSEMBLY) -#if defined(__PRE_RAM__) -#else +#include <cpu/amd/gx2def.h> + +/* northbridge.c */ unsigned int gx2_scan_root_bus(device_t root, unsigned int max); int sizeram(void); +void do_vsmbios(void); void graphics_init(void); -void northbridgeinit(void); -#endif -#endif + +/* northbridgeinit.c */ +void northbridge_init_early(void); +uint32_t get_systop(void);
#endif /* NORTHBRIDGE_AMD_GX2_H */
Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridgeinit.c Wed Dec 29 22:02:50 2010 (r6220) +++ trunk/src/northbridge/amd/gx2/northbridgeinit.c Wed Dec 29 22:12:10 2010 (r6221) @@ -23,25 +23,25 @@ };
struct gliutable gliu0table[] = { - {.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ - {.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ - {.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ - {.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=GLIU0_P2D_BM_0, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name=GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ + {.desc_name=GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ + {.desc_name=GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=GLIU0_P2D_BMO_1, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ {.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU}, {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, };
struct gliutable gliu1table[] = { - {.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ - {.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc */ - {.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ - {.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ - {.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=GLIU1_P2D_BM_0,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name=GLIU1_P2D_BM_1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc */ + {.desc_name=GLIU1_P2D_SC_0,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ + {.desc_name=GLIU1_P2D_R_0,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=GLIU1_P2D_BM_4,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=GLIU1_P2D_BM_3,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ {.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0}, - {.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */ + {.desc_name=GLIU1_IOD_SC_0,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */ {.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0}, };
@@ -98,8 +98,7 @@ {GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority. */ {GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0027}}, /* GLPCI Priority + PID */ {GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID */ - {VIP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* VIP PID */ - {AES_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0013}}, /* AES PID */ + {FG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* FG PID */ {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */ };
@@ -511,7 +510,7 @@ static uint64_t getShadow(void) { msr_t msr; - msr = rdmsr(MSR_GLIU0_SHADOW); + msr = rdmsr(GLIU0_P2D_SC_0); return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo; }
@@ -694,8 +693,32 @@ wrmsr(CPU_RCONF_BYPASS, msr); }
+uint32_t get_systop(void) +{ + struct gliutable *gl = 0; + uint32_t systop; + msr_t msr; + int i; + + for (i = 0; gliu0table[i].desc_name != GL_END; i++) { + if (gliu0table[i].desc_type == R_SYSMEM) { + gl = &gliu0table[i]; + break; + } + } + if (gl) { + msr = rdmsr(gl->desc_name); + systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8); + systop += 0x1000; /* 4K */ + } else { + systop = + ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024; + } + return systop; +} + /* Core Logic initialization: Host bridge. */ -void northbridgeinit(void) +void northbridge_init_early(void) { msr_t msr; int i;
Modified: trunk/src/southbridge/amd/cs5535/cs5535.h ============================================================================== --- trunk/src/southbridge/amd/cs5535/cs5535.h Wed Dec 29 22:02:50 2010 (r6220) +++ trunk/src/southbridge/amd/cs5535/cs5535.h Wed Dec 29 22:12:10 2010 (r6221) @@ -70,6 +70,7 @@ #define ATA_SB_GLD_MSR_CONF (MSR_SB_ATA + 0x01) #define ATA_SB_GLD_MSR_ERR (MSR_SB_ATA + 0x03) #define ATA_SB_GLD_MSR_PM (MSR_SB_ATA + 0x04) +#define ATA_SB_IDE_CFG (MSR_SB_ATA + 0x10)
/* AC97 */ #define AC97_SB_GLD_MSR_CONF (MSR_SB_AC97 + 0x01)
* repository service svn@coreboot.org [101229 22:12]:
Author: myles Date: Wed Dec 29 22:12:10 2010 New Revision: 6221 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6221
Log: -Change the remaining GLIU1 port 5 register names from VIP (Video Input Port) to FG (FooGlue). As the GX2 has no VIP port. -Change the Memmory setup MSR register names so they correspond better to the databook. (Part1) This is less confusing for beginners. -Add a MSR printing function to northbridge.c like in the Geode LX code. -Remove the AES register names.(GX2 has no AES registers) -Delete some unused code. -Clean up GX2 northbridge code to match Geode LX code. -Add missing copyright header to northbridge.c. -Move hardcoded IRQ defining from northbridge.c to irq_tables.c .
Signed-off-by: Nils Jacobs njacobs8@hetnet.nl Acked-by: Myles Watson mylesgw@gmail.com
Any idea why this broke the lippert frontrunner?
http://qa.coreboot.org/log_buildbrd.php?revision=6222&device=frontrunner...
Op donderdag 30 december 2010 18:50:48 schreef u:
- repository service svn@coreboot.org [101229 22:12]:
Author: myles Date: Wed Dec 29 22:12:10 2010 New Revision: 6221 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6221
Log: -Change the remaining GLIU1 port 5 register names from VIP (Video Input Port)
to FG (FooGlue). As the GX2 has no VIP port.-Change the Memmory setup MSR register names so they correspond better to the
databook. (Part1) This is less confusing for beginners.-Add a MSR printing function to northbridge.c like in the Geode LX code. -Remove the AES register names.(GX2 has no AES registers) -Delete some unused code. -Clean up GX2 northbridge code to match Geode LX code. -Add missing copyright header to northbridge.c. -Move hardcoded IRQ defining from northbridge.c to irq_tables.c .
Signed-off-by: Nils Jacobs njacobs8@hetnet.nl Acked-by: Myles Watson mylesgw@gmail.com
Any idea why this broke the lippert frontrunner?
http://qa.coreboot.org/log_buildbrd.php?revision=6222&device=frontrunner... ndor=lippert&num=2
See previous message. My older patch was not yet committed. And as i stated in the patchset i tested ABUILD and boottest in combination with my previous patches.
Thanks, Nils.
-
Nils -
repository service -
Stefan Reinauer