Eric,
Without hard_reset, s2885 is ok now.
In the k8/cpufixup.c need compare mmio_basek and 0x3f0000 and then assign that to TOM.
Regards
YH
-----邮件原件----- 发件人: YhLu 发送时间: 2003年9月4日 12:44 收件人: ebiederman@lnxi.com 抄送: Stefan Reinauer; LinuxBIOS 主题: Re: [COMMIT] Infrastructure Updates 4
Eric,
If I disable the hard_reset, it can enumerate from link2 to link0. And the 8131 on link2 and 8151 on link0 all show out.
Maybe you can add MACRO to control reverse scan for AMKK8 northbridge. ( link2 then link0)
But it continues to reboot.
Regards
Yinghai Lu
Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.42.0_Fallback Thu Sep 4 19:17:58 EDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... dev->links= 3 Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7450] bus ops PCI: 01:01.0 [1022/7450] enabled PCI: 01:01.1 [1022/7451] ops PCI: 01:01.1 [1022/7451] enabled PCI: 01:02.0 [1022/7450] bus ops PCI: 01:02.0 [1022/7450] enabled PCI: 01:02.1 [1022/7451] ops PCI: 01:02.1 [1022/7451] enabled PCI: 01:03.0 [1022/7460] enabled PCI: 01:04.0 [1022/7468] bus ops PCI: 01:04.0 [1022/7468] enabled PCI: 01:04.1 [1022/7469] ops PCI: 01:04.1 [1022/7469] enabled PCI: 01:04.2 [1022/746a] enabled PCI: 01:04.3 [1022/746b] ops PCI: 01:04.3 [1022/746b] enabled PCI: 01:04.5 [1022/746d] enabled PCI: 01:04.6 [1022/746e] enabled PCI: pci_scan_bus for bus 2 PCI: 02:09.0 [14e4/16a7] ops PCI: 02:09.0 [14e4/16a7] enabled PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: pci_scan_bus returning with max=03 PCI: pci_scan_bus for bus 4 PCI: 04:00.0 [1022/7464] ops PCI: 04:00.0 [1022/7464] enabled PCI: 04:00.1 [1022/7464] ops PCI: 04:00.1 [1022/7464] enabled PCI: 04:00.2 [1022/7463] ops PCI: 04:00.2 [1022/7463] enabled PCI: 04:01.0 [1022/7462] enabled PCI: 04:0b.0 [1095/3114] ops PCI: 04:0b.0 [1095/3114] enabled PCI: 04:0c.0 [104c/8023] ops PCI: 04:0c.0 [104c/8023] enabled PCI: pci_scan_bus returning with max=04 PCI: pci_scan_bus returning with max=04 Hyper transport scan link: 2 new max: 0 Hypertransport scan link done Hyper transport scan link: 0 max: 5 PCI: 05:01.0 [1022/7454] enabled next_unitid: 0004 Hypertransport link capability not foundPCI: pci_scan_bus for bus 5 PCI: 05:00.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring. PCI: 05:00.0 No device operations PCI: 05:01.0 [1022/7454] ops PCI: 05:01.0 [1022/7454] enabled PCI: 05:02.0 [1022/7455] bus ops PCI: 05:02.0 [1022/7455] enabled Copying LinuxBIOS to ram.
-----邮件原件----- 发件人: YhLu 发送时间: 2003年9月4日 10:48 收件人: ebiederman@lnxi.com 抄送: Stefan Reinauer; LinuxBIOS 主题: re: [COMMIT] Infrastructure Updates 4
Eric,
In the hypertransport_scan_chain, if the hard_reset is needed, it may produce problem.
Hard_reset call 8111 LPC (B1, D4, F0) reg 0x47 to trigger Reset.
But it is called before pci_scan_bus. At that time the 8111 LPC is still unkown.
Regards
YH
-----邮件原件----- 发件人: YhLu 发送时间: 2003年9月4日 10:30 收件人: 'ebiederman@lnxi.com' 抄送: Stefan Reinauer; LinuxBIOS 主题: Re: [COMMIT] Infrastructure Updates 4
I still have problems for s2885.
Amdk8_scan_bus for MC0 only from link0 to link2. link0 is connected to 8151 and link2 is connected to 8131.
Then it reboot again and agin.
After I reverse the scan from link2 to link0. It can scan out 8131 and 8111 but hung after "HyperT reset needed" is printed. Maybe the reset.c that I move from hdama got some problems.
YH.
LinuxBIOS-1.1.42.0_Fallback Thu Sep 4 17:07:56 EDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... dev->links= 3 Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed
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* YhLu YhLu@tyan.com [030906 04:58]:
Eric,
Without hard_reset, s2885 is ok now.
Did you have a look at the implementation of hard_reset in reset.c? void hard_reset(void) { set_bios_reset(); pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1); }
It looks like if the bus numbering for a mainboard is different, the device (southbridge?) has to be changed here as well. Can this device id somehow be moved to the config file, or generated with the already known config parameters?
Stefan
On Mon, 8 Sep 2003, Stefan Reinauer wrote:
- YhLu YhLu@tyan.com [030906 04:58]:
Eric,
Without hard_reset, s2885 is ok now.
Did you have a look at the implementation of hard_reset in reset.c? void hard_reset(void) { set_bios_reset(); pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1); }
the only reset.c I see is in the mainboard-specific code. Nevertheless this code really should do the find_device thing.
on the list of fixes.
ron
* ron minnich rminnich@lanl.gov [030908 17:03]:
On Mon, 8 Sep 2003, Stefan Reinauer wrote:
Did you have a look at the implementation of hard_reset in reset.c? void hard_reset(void) { set_bios_reset(); pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1); }
the only reset.c I see is in the mainboard-specific code. Nevertheless this code really should do the find_device thing.
I don't think that the wrong device is used though: 01:04.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8111 PCI (rev 07) PCI: 01:04.0 [1022/7460] enabled
Stefan
YhLu YhLu@tyan.com writes:
Eric,
Without hard_reset, s2885 is ok now.
In the k8/cpufixup.c need compare mmio_basek and 0x3f0000 and then assign that to TOM.
Hmm. What is special about 0x3f0000?
In any event this sounds promising. It looks like the reset needs to move a little farther down in the code until after all of the hypertransport chains have been enumerated.
Eric
-
ebiederman＠lnxi.com -
ron minnich -
Stefan Reinauer -
YhLu