Dear coreboot folks,
could somebody please test commit »cpu/x86/mtrr/mtrr.c: Remove superfluous assignment to `type_index`« [1] as today I broke my ASRock E350M1 board booting with coreboot including this patch. I am not sure though as I also changed the SeaBIOS payload applying the patch series »Convert AHCI driver to run entirely in 32bit mode« [2].
Kevin O'Connor (6): Rearrange stack_hop_back() call in wait_irq, check_irqs, and _farcall16. Minor - move call16 assembler in romlayout.S. Make __call16 use C calling convention and support two passed parameters. Update _farcall16() to pass segment of callregs explicitly. Support call16() calls after entering 32bit mode from call32(). Run ahci code entirely in 32bit mode.
Makefile | 4 +- src/block.c | 13 ++++-- src/hw/ahci.c | 15 ++----- src/hw/blockcmd.c | 5 ++- src/romlayout.S | 132 ++++++++++++++++++++++++++++++++---------------------- src/stacks.c | 78 +++++++++++++++++++------------- 6 files changed, 145 insertions(+), 102 deletions(-)
coreboot runs through just fine and then SeaBIOS halts at `mtrr init` when build with serial console and debug level 8.
Using the SeaBIOS payload built with no serial console, it seems, that the board just reset and just hang.
Bot logs captured with `readserial.py` are attached.
Thanks,
Paul
[1] http://review.coreboot.org/3953 [2] http://www.coreboot.org/pipermail/seabios/2013-October/007040.html
Dear coreboot folks,
Am Freitag, den 04.10.2013, 11:56 +0200 schrieb Paul Menzel:
could somebody please test commit »cpu/x86/mtrr/mtrr.c: Remove superfluous assignment to `type_index`« [1] as today I broke my ASRock E350M1 board booting with coreboot including this patch. I am not sure though as I also changed the SeaBIOS payload applying the patch series »Convert AHCI driver to run entirely in 32bit mode« [2].
[…]
Kevin told me in #coreboot on <irc.freenote.net> that I built SeaBIOS for QEMU and not coreboot. I am not sure how that happened and why my old config was ignored, but it is good to know the reason.
Thanks,
Paul