Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/800
-gerrit
commit 995c74c88e546bbff6b625860d82fddcf60275c2 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Fri Mar 16 20:39:10 2012 +0200
Rename bootblock init functions
The following chip-specific functions were renamed to include chip name in the function: - bootblock_northbridge_init - bootblock_southbridge_init
Change-Id: I54620a32d0799ef420b8b18772426f8d8082d4ca Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/mainboard/hp/dl165_g6_fam10/bootblock.c | 4 ++-- src/northbridge/amd/amdfam10/bootblock.c | 2 +- src/northbridge/amd/amdk8/bootblock.c | 2 +- src/southbridge/amd/amd8111/bootblock.c | 2 +- src/southbridge/amd/cimx/sb700/bootblock.c | 2 +- src/southbridge/amd/cimx/sb800/bootblock.c | 2 +- src/southbridge/amd/cimx/sb900/bootblock.c | 2 +- src/southbridge/amd/sb600/bootblock.c | 2 +- src/southbridge/amd/sb700/bootblock.c | 2 +- src/southbridge/amd/sb800/bootblock.c | 2 +- src/southbridge/broadcom/bcm5785/bootblock.c | 2 +- src/southbridge/intel/i82371eb/bootblock.c | 2 +- src/southbridge/intel/i82801gx/bootblock.c | 2 +- src/southbridge/nvidia/ck804/bootblock.c | 2 +- src/southbridge/nvidia/mcp55/bootblock.c | 2 +- src/southbridge/sis/sis966/bootblock.c | 2 +- src/southbridge/via/vt8237r/bootblock.c | 2 +- util/sconfig/main.c | 4 ++-- 18 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c index dfece95..e7c0680 100644 --- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c +++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c @@ -49,8 +49,8 @@ void shc4307_init(void) static unsigned long init_mainboard(int bsp_cpu) { if (!bsp_cpu) return 0; - bootblock_northbridge_init(); - //bootblock_southbridge_init(); + init_northbridge_amd_amdfam10(); + //init_southbridge_broadcom_bcm5785(); shc4307_init(); return 0; } diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c index 612004a..328e9ad 100644 --- a/src/northbridge/amd/amdfam10/bootblock.c +++ b/src/northbridge/amd/amdfam10/bootblock.c @@ -3,7 +3,7 @@ #include <device/pci_def.h> #include "northbridge/amd/amdfam10/early_ht.c"
-static void bootblock_northbridge_init(void) { +static void init_northbridge_amd_amdfam10(void) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ diff --git a/src/northbridge/amd/amdk8/bootblock.c b/src/northbridge/amd/amdk8/bootblock.c index b5395bb..8afd507 100644 --- a/src/northbridge/amd/amdk8/bootblock.c +++ b/src/northbridge/amd/amdk8/bootblock.c @@ -3,6 +3,6 @@ #include <device/pci_def.h> #include "northbridge/amd/amdk8/early_ht.c"
-static void bootblock_northbridge_init(void) { +static void init_northbridge_amd_amdk8(void) { enumerate_ht_chain(); } diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index 3009c0b..d4660de 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -41,7 +41,7 @@ static void amd8111_enable_rom(void) pci_io_write_config8(dev, 0x43, byte); }
-static void bootblock_southbridge_init(void) +static void init_southbridge_amd_amd8111(void) { amd8111_enable_rom(); } diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 401c039..657fbdd 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -90,7 +90,7 @@ static void sb700_enable_rom(void) pci_io_write_config16(dev, 0x6c, word); }
-static void bootblock_southbridge_init(void) +static void init_southbridge_amd_cimx_sb700(void) { /* Setup the rom access for 2M */ sb700_enable_rom(); diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 0a339b0..9e00219 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -104,7 +104,7 @@ static void enable_clocks(void) *acpi_mmio = reg32; }
-static void bootblock_southbridge_init(void) +static void init_southbridge_amd_cimx_sb800(void) { /* Setup the rom access for 2M */ enable_rom(); diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index e84743b..f3b53d0 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -90,7 +90,7 @@ static void sb900_enable_rom(void) pci_io_write_config16(dev, 0x6c, word); }
-static void bootblock_southbridge_init(void) +static void init_southbridge_amd_cimx_sb900(void) { /* Setup the rom access for 2M */ sb900_enable_rom(); diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c index 45991ee..0184f73 100644 --- a/src/southbridge/amd/sb600/bootblock.c +++ b/src/southbridge/amd/sb600/bootblock.c @@ -64,7 +64,7 @@ static void sb600_enable_rom(void) pci_io_write_config16(dev, 0x6e, 0xffff); }
-static void bootblock_southbridge_init(void) +static void init_southbridge_amd_sb600(void) { sb600_enable_rom(); } diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index 370cff9..b4bb686 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -64,7 +64,7 @@ static void sb700_enable_rom(void) pci_io_write_config16(dev, 0x6e, 0xffff); }
-static void bootblock_southbridge_init(void) +static void init_southbridge_amd_sb700(void) { sb700_enable_rom(); } diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c index 30d6ac6..6245dca 100644 --- a/src/southbridge/amd/sb800/bootblock.c +++ b/src/southbridge/amd/sb800/bootblock.c @@ -62,7 +62,7 @@ static void sb800_enable_rom(void) pci_io_write_config16(dev, 0x6e, 0xffff); }
-static void bootblock_southbridge_init(void) +static void init_southbridge_amd_sb800(void) { sb800_enable_rom(); } diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index cadda53..e1e5f31 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -38,7 +38,7 @@ static void bcm5785_enable_rom(void) pci_write_config8(dev, 0x41, byte); }
-static void bootblock_southbridge_init(void) +static void init_southbridge_broadcom_bcm5785(void) { bcm5785_enable_rom(); } diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 07fa0bc..a875723 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -48,7 +48,7 @@ static void i82371eb_enable_rom(void) pci_write_config16(dev, XBCS, reg16); }
-static void bootblock_southbridge_init(void) +static void init_southbridge_intel_i82371eb(void) { i82371eb_enable_rom(); } diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 39b0bd4..a0f73b3 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -33,7 +33,7 @@ static void enable_spi_prefetch(void) pci_write_config8(dev, 0xdc, reg8); }
-static void bootblock_southbridge_init(void) +static void init_southbridge_intel_i82801gx(void) { enable_spi_prefetch(); } diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index 29c10c8..3175606 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -42,7 +42,7 @@ static void ck804_enable_rom(void) pci_write_config8(addr, 0x88, byte); }
-static void bootblock_southbridge_init(void) +static void init_southbridge_nvidia_ck804(void) { ck804_enable_rom(); } diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index affb025..6fb6dbb 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -53,7 +53,7 @@ static void mcp55_enable_rom(void) pci_write_config16(addr, 0x90, word); }
-static void bootblock_southbridge_init(void) +static void init_southbridge_nvidia_mcp55(void) { mcp55_enable_rom(); } diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c index 1ff3cda..45ab81b 100644 --- a/src/southbridge/sis/sis966/bootblock.c +++ b/src/southbridge/sis/sis966/bootblock.c @@ -41,7 +41,7 @@ static void sis966_enable_rom(void) pci_write_config8(addr, 0x40, pci_read_config8(addr, 0x40) | 0x11); }
-static void bootblock_southbridge_init(void) +static void init_southbridge_sis_sis966(void) { sis966_enable_rom(); } diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c index 8df37aa..0ca0533 100644 --- a/src/southbridge/via/vt8237r/bootblock.c +++ b/src/southbridge/via/vt8237r/bootblock.c @@ -21,7 +21,7 @@ #include <arch/romcc_io.h> #include <device/pci_ids.h>
-static void bootblock_southbridge_init(void) +static void init_southbridge_via_vt8237r(void) { device_t dev; /* don't walk other busses, HT is not enabled */ diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 4e3479b..21105f4 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -595,9 +595,9 @@ int main(int argc, char** argv) { h = &headers; while (h->next) { h = h->next; - char * buf = translate_name(h->name, SPLIT_1ST); + char * buf = translate_name(h->name, TO_LOWER); if (buf) { - fprintf(autogen, "\tbootblock_%s_init();\n", buf); + fprintf(autogen, "\tinit_%s();\n", buf); free(buf); } }
we made a decision in the early days to NOT include the chip part name in the function names. This was not a mistake or omission, it was a deliberate design choice.
The reason to name things this way is because a board is composed of a set of parts, and the partname is in the file name path. Hence, the board can be constructed of files calling functions with generic names, and the generic functions are provided by files chosen in the config. In some cases, it has proven trivial to port a mainboard to a new chipset by changing only the config to use a different chip. The fact that the function name did not include the chipname made this trivial.
If we think that we really need the chip name in the function, ok, but it's a change in the way we designed the build process. Maybe it's a change we have to make. I am not yet convinced.
thanks
ron
-
Kyösti Mälkki -
ron minnich