[RFC] Getting CAR to work on P6 family; Port SECC P6 L2 cache initialization code to where?
Hi all, this is a RFC.
While Joseph, Idwer and myself convened on IRC for the past two days trying to get CAR working on the P6 family of CPUs, we found that -
The Intel CAR code works as is on Tualatin cores, L2 cache fully enabled The same code works for me on a Katmai, but only L1 cache is enabled This code does not boot at all for Idwer who also has a Katmai, and has stumped everyone We need to port a piece of long code from coreboot v1 that initializes the off-chip L2 cache found on Klamath/Deschutes/Katmai CPUs. They are respectively models 63x,65x and 67x. 16k of L1 is enough. We're only using 4k for CAR on Intel.
It was written in C. I looked at the OEM BIOS for P2B-LS and L2 is initialized from the "inner BIOS", like the RAM stage of coreboot, when RAM is fully up and running. This means this can go into model_6xx_init(), which is prefereable as I just need to make enough adjustments to make it work again.
Joseph OTOH suggests that I should port this code into cache_as_ram.inc which is much earlier, actually before motherboard romstage. This code is assembly, meaning I'll need to port this thing back to assembly.
Question is: Where should I port this code to? CPU driver, or cache_as_ram.inc?
A patch to separate model 67x from model 6xx will soon come, either from me or Joseph. A similar one could be done for 65x and 63x. I do not have 66x Celerons to test so I cannot ascertain if this special attention will be needed for them.
Thanks Keith
On 05/09/2010 01:33 AM, Keith Hui wrote:
Hi all, this is a RFC.
While Joseph, Idwer and myself convened on IRC for the past two days trying to get CAR working on the P6 family of CPUs, we found that -
The Intel CAR code works as is on Tualatin cores, L2 cache fully enabled The same code works for me on a Katmai, but only L1 cache is enabled This code does not boot at all for Idwer who also has a Katmai, and has stumped everyone We need to port a piece of long code from coreboot v1 that initializes the off-chip L2 cache found on Klamath/Deschutes/Katmai CPUs. They are respectively models 63x,65x and 67x. 16k of L1 is enough. We're only using 4k for CAR on Intel.
It was written in C. I looked at the OEM BIOS for P2B-LS and L2 is initialized from the "inner BIOS", like the RAM stage of coreboot, when RAM is fully up and running. This means this can go into model_6xx_init(), which is prefereable as I just need to make enough adjustments to make it work again.
Joseph OTOH suggests that I should port this code into cache_as_ram.inc which is much earlier, actually before motherboard romstage. This code is assembly, meaning I'll need to port this thing back to assembly.
Question is: Where should I port this code to? CPU driver, or cache_as_ram.inc?
Hmm, I guess it does not really need to be done in cache_as_ram if the 16k is large enough to get things going.
So if it would be easier I would suggest early in model_6*x_init(). Especially if the vendor bios enables it post raminit.
On 5/9/10 7:33 AM, Keith Hui wrote:
Joseph OTOH suggests that I should port this code into cache_as_ram.inc which is much earlier, actually before motherboard romstage. This code is assembly, meaning I'll need to port this thing back to assembly.
Question is: Where should I port this code to? CPU driver, or cache_as_ram.inc?
If there are no penalties for putting it in the CPU driver, put it there. If you run without cache until the CPU driver is executed otherwise (and that makes a measurable difference of several ms) you might want to do this earlier
Stefan
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Joseph Smith -
Keith Hui -
Stefan Reinauer