Hi everyone,
I was going to try coreboot on an ASROCK FM2A88X Extreme4+ ( https://www.asrock.com/mb/AMD/FM2A88X%20Extreme4+/) with the configuration of the supported ASUS A88XM-E ( https://doc.coreboot.org/mainboard/asus/a88xm-e.html) which has the same chipset (A88X Bolton). The fact is that, at this moment, I only have a 16 MiB flash, while the image is 8 MiB. As the chipset claims that it “Supports a maximum SPI ROM size of 16MB” I think there should be no problem, but I wonder how I have to burn the image. That led me to the question of how the translation between CPU and flash addresses are done. For supporting various ROM sizes, I guess the controller should somehow know the size of the ROM, but I don't see anywhere where that could be specified. The only thing I found is this stack overflow question ( https://stackoverflow.com/questions/60200796/how-does-processor-read-bios-fr...). There, flash descriptors and some straps are mentioned to provide the ROM size, but none of those methods are mentioned on the Bolton Datasheet. So I have two questions here, 1. How should I burn the 8 MiB image on the 16 MiB flash? 2. Out of curiosity, how is the cpu-flash address translation done?
Dear Pedro,
Am 06.08.22 um 18:45 schrieb Pedro Erencia:
I was going to try coreboot on an ASROCK FM2A88X Extreme4+ ( https://www.asrock.com/mb/AMD/FM2A88X%20Extreme4+/) with the configuration of the supported ASUS A88XM-E ( https://doc.coreboot.org/mainboard/asus/a88xm-e.html) which has the same chipset (A88X Bolton).
Welcome to coreboot. There is a very small chance, that using an image from another board might damage the board due to GPIOs being misconfigured, and a short-circuit is programmed.
The fact is that, at this moment, I only have a 16 MiB flash, while the image is 8 MiB. As the chipset claims that it “Supports a maximum SPI ROM size of 16MB” I think there should be no problem, but I wonder how I have to burn the image. That led me to the question of how the translation between CPU and flash addresses are done. For supporting various ROM sizes, I guess the controller should somehow know the size of the ROM, but I don't see anywhere where that could be specified.
In `make menuconfig` in the section *Mainboard* adapt
ROM chip size (8192 KB (8 MB)) --->
to 16 MB. But it might be useful to also adapt the size for the CBFS filesystem in ROM. (It’s automatically adapted if you delete `.config` beforehand.)
In the past, taking the 8 MB file, and concatenating it twice to a 16 MB image also worked.
[…]
Kind regards,
Paul
Hi Pedro,
On 06.08.22 18:45, Pedro Erencia wrote:
I was going to try coreboot on an ASROCK FM2A88X Extreme4+ ( https://www.asrock.com/mb/AMD/FM2A88X%20Extreme4+/) with the configuration of the supported ASUS A88XM-E ( https://doc.coreboot.org/mainboard/asus/a88xm-e.html) which has the same chipset (A88X Bolton).
to repeat Paul's warning: A coreboot build is very board specific. There's a chance that it boots, but there's also a chance that some hardware breaks. The chance that everything works OOB is probably lower.
The fact is that, at this moment, I only have a 16 MiB flash, while the image is 8 MiB. As the chipset claims that it “Supports a maximum SPI ROM size of 16MB” I think there should be no problem, but I wonder how I have to burn the image. That led me to the question of how the translation between CPU and flash addresses are done. For supporting various ROM sizes, I guess the controller should somehow know the size of the ROM, but I don't see anywhere where that could be specified. The only thing I found is this stack overflow question ( https://stackoverflow.com/questions/60200796/how-does-processor-read-bios-fr...). There, flash descriptors and some straps are mentioned to provide the ROM size, but none of those methods are mentioned on the Bolton Datasheet. So I have two questions here,
- How should I burn the 8 MiB image on the 16 MiB flash?
- Out of curiosity, how is the cpu-flash address translation done?
You are right that it's not explicitly configured. It's a simple trick: If you don't know the size you have to start at an offset from one end. For the lower end (address 0) that's simple, every SPI flash starts at address 0. But x86 is very special: The firmware actually starts at the end of the flash. And that's where one details plays a significant role: A SPI flash ignores address bits that it doesn't know. So, when it is asked for data at address 0xfffff0, it will always return the last 16 bytes (assuming a flash chip that uses commands with 24-bit addresses). The size of the chip doesn't matter, a 1MiB chip would simply ignore the 4 most-significant address bits.
Before SPI flash, the logic was in the flash chip itself, AIUI. The chips were on the memory bus and knew they should reply to requests in the range 0x100000000-flashsize..0xffffffff.
Nico
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Nico Huber -
Paul Menzel -
Pedro Erencia