Hi everyone,

I was going to try coreboot on an ASROCK FM2A88X Extreme4+ (https://www.asrock.com/mb/AMD/FM2A88X%20Extreme4+/) with the configuration of the supported ASUS A88XM-E (https://doc.coreboot.org/mainboard/asus/a88xm-e.html) which has the same chipset (A88X Bolton).
The fact is that, at this moment, I only have a 16 MiB flash, while the image is 8 MiB. As the chipset claims that it
“Supports a maximum SPI ROM size of 16MB” I think there should be no problem, but I wonder how I have to burn the image. That led me to the question of how the translation between CPU and flash addresses are done. For supporting various ROM sizes, I guess the controller should somehow know the size of the ROM, but I don't see anywhere where that could be specified.
The only thing I found is this stack overflow question (https://stackoverflow.com/questions/60200796/how-does-processor-read-bios-from-spi-flash). There, flash descriptors and some straps are mentioned to provide the ROM size, but none of those methods are mentioned on the Bolton Datasheet.
So I have two questions here,
1. How should I burn the 8 MiB image on the 16 MiB flash?
2. Out of curiosity, how is the cpu-flash address translation done?