Intel ICH5 is very similar to its predecessor - ICH4. There are small differences are in power-management registers.
Signed-off-by: Michał Mirosław mirq-linux@rere.qmqm.pl
Index: util/inteltool/gpio.c =================================================================== --- util/inteltool/gpio.c (wersja 3826) +++ util/inteltool/gpio.c (kopia robocza) @@ -119,6 +119,7 @@ gpio_registers = ich7_gpio_registers; size = ARRAY_SIZE(ich7_gpio_registers); break; + case PCI_DEVICE_ID_INTEL_ICH5: case PCI_DEVICE_ID_INTEL_ICH4: case PCI_DEVICE_ID_INTEL_ICH4M: gpiobase = pci_read_word(sb, 0x58) & 0xfffc; Index: util/inteltool/inteltool.h =================================================================== --- util/inteltool/inteltool.h (wersja 3826) +++ util/inteltool/inteltool.h (kopia robocza) @@ -37,6 +37,7 @@ #define PCI_DEVICE_ID_INTEL_ICH2 0x2440 #define PCI_DEVICE_ID_INTEL_ICH4 0x24c0 #define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc +#define PCI_DEVICE_ID_INTEL_ICH5 0x24d0 #define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0 #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 Index: util/inteltool/powermgt.c =================================================================== --- util/inteltool/powermgt.c (wersja 3826) +++ util/inteltool/powermgt.c (kopia robocza) @@ -21,6 +21,56 @@ #include <stdio.h> #include "inteltool.h"
+static const io_register_t ich5_pm_registers[] = { + { 0x00, 2, "PM1_STS" }, + { 0x02, 2, "PM1_EN" }, + { 0x04, 4, "PM1_CNT" }, + { 0x08, 4, "PM1_TMR" }, + { 0x0c, 4, "RESERVED" }, + { 0x10, 4, "PROC_CNT" }, + { 0x14, 4, "RESERVED" }, + { 0x18, 4, "RESERVED" }, + { 0x1c, 4, "RESERVED" }, + { 0x20, 4, "RESERVED" }, + { 0x24, 4, "RESERVED" }, + { 0x28, 4, "GPE0_STS" }, + { 0x2C, 4, "GPE0_EN" }, + { 0x30, 4, "SMI_EN" }, + { 0x34, 4, "SMI_STS" }, + { 0x38, 2, "ALT_GP_SMI_EN" }, + { 0x3a, 2, "ALT_GP_SMI_STS" }, + { 0x3c, 4, "RESERVED" }, + { 0x40, 2, "MON_SMI" }, + { 0x42, 2, "RESERVED" }, + { 0x44, 2, "DEVACT_STS" }, + { 0x46, 2, "RESERVED" }, + { 0x48, 2, "DEVTRAP_EN" }, + { 0x4a, 2, "RESERVED" }, + { 0x4c, 4, "RESERVED" }, + { 0x50, 4, "RESERVED" }, + { 0x54, 4, "RESERVED" }, + { 0x58, 4, "RESERVED" }, + { 0x5c, 4, "RESERVED" }, + /* Here start the TCO registers */ + { 0x60, 1, "TCO_RLD" }, + { 0x61, 1, "TCO_TMR" }, + { 0x62, 1, "TCO_DAT_IN" }, + { 0x63, 1, "TCO_DAT_OUT" }, + { 0x64, 2, "TCO1_STS" }, + { 0x66, 2, "TCO2_STS" }, + { 0x68, 2, "TCO1_CNT" }, + { 0x6a, 2, "TCO2_CNT" }, + { 0x6c, 2, "TCO_MESSAGE" }, + { 0x6e, 1, "TCO_WDCNT" }, + { 0x6f, 1, "RESERVED" }, + { 0x70, 1, "SW_IRQ_GEN" }, + { 0x71, 1, "RESERVED" }, + { 0x72, 2, "RESERVED" }, + { 0x74, 4, "RESERVED" }, + { 0x78, 4, "RESERVED" }, + { 0x7c, 4, "RESERVED" }, +}; + static const io_register_t ich7_pm_registers[] = { { 0x00, 2, "PM1_STS" }, { 0x02, 2, "PM1_EN" }, @@ -154,6 +204,11 @@ printf("\n============= PMBASE ============\n\n");
switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_ICH5: + pmbase = pci_read_word(sb, 0x40) & 0xfffc; + pm_registers = ich5_pm_registers; + size = ARRAY_SIZE(ich5_pm_registers); + break; case PCI_DEVICE_ID_INTEL_ICH7: case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: Index: util/inteltool/rootcmplx.c =================================================================== --- util/inteltool/rootcmplx.c (wersja 3826) +++ util/inteltool/rootcmplx.c (kopia robocza) @@ -42,6 +42,7 @@ case PCI_DEVICE_ID_INTEL_ICH0: case PCI_DEVICE_ID_INTEL_ICH4: case PCI_DEVICE_ID_INTEL_ICH4M: + case PCI_DEVICE_ID_INTEL_ICH5: printf("This southbridge does not have RCBA.\n"); return 1; default: Index: util/inteltool/inteltool.c =================================================================== --- util/inteltool/inteltool.c (wersja 3826) +++ util/inteltool/inteltool.c (kopia robocza) @@ -40,6 +40,7 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH5, "ICH5" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
On Sat, Dec 20, 2008 at 06:04:58PM +0100, Michał Mirosław wrote: [cut: patch]
And here's a dump from P4-based (Northwood,HT) HP compaq nx9500 laptop. Just in in case you need the data.
Intel CPU: Family f, Model 2 Intel Northbridge: 8086:2570 (i865P) Intel Southbridge: 8086:24d0 (ICH5)
============= GPIOS =============
GPIOBASE = 0x1180 (IO)
gpiobase+0x0000: 0x1ae03980 (GPIO_USE_SEL) gpiobase+0x0004: 0x0000ffff (GP_IO_SEL) gpiobase+0x0008: 0x00000000 (RESERVED) gpiobase+0x000c: 0x1bff0000 (GP_LVL) gpiobase+0x0010: 0x00000000 (RESERVED) gpiobase+0x0014: 0x00000000 (GPO_TTL) gpiobase+0x0018: 0x00040000 (GPO_BLINK) gpiobase+0x001c: 0x00000000 (RESERVED) gpiobase+0x0020: 0x00000000 (RESERVED) gpiobase+0x0024: 0x00000000 (RESERVED) gpiobase+0x0028: 0x00000000 (RESERVED) gpiobase+0x002c: 0x00002900 (GPI_INV) gpiobase+0x0030: 0x00000007 (GPIO_USE_SEL2) gpiobase+0x0034: 0x00000300 (GP_IO_SEL2) gpiobase+0x0038: 0x00030303 (GP_LVL2) gpiobase+0x003c: 0x00000000 (RESERVED)
============= RCBA ==============
This southbridge does not have RCBA.
============= PMBASE ============
PMBASE = 0x1000 (IO)
pmbase+0x0000: 0x0411 (PM1_STS) pmbase+0x0002: 0x0120 (PM1_EN) pmbase+0x0004: 0x00001c01 (PM1_CNT) pmbase+0x0008: 0x00dba3bd (PM1_TMR) pmbase+0x000c: 0x00000000 (RESERVED) pmbase+0x0010: 0x000000c0 (PROC_CNT) pmbase+0x0014: 0x00000000 (RESERVED) pmbase+0x0018: 0x00000000 (RESERVED) pmbase+0x001c: 0x00000000 (RESERVED) pmbase+0x0020: 0x00000000 (RESERVED) pmbase+0x0024: 0x00000000 (RESERVED) pmbase+0x0028: 0xd67f0000 (GPE0_STS) pmbase+0x002c: 0x20000000 (GPE0_EN) pmbase+0x0030: 0x00000033 (SMI_EN) pmbase+0x0034: 0x00004900 (SMI_STS) pmbase+0x0038: 0x2100 (ALT_GP_SMI_EN) pmbase+0x003a: 0xfe7f (ALT_GP_SMI_STS) pmbase+0x003c: 0x00000000 (RESERVED) pmbase+0x0040: 0x0100 (MON_SMI) pmbase+0x0042: 0x0000 (RESERVED) pmbase+0x0044: 0x3eef (DEVACT_STS) pmbase+0x0046: 0x0000 (RESERVED) pmbase+0x0048: 0x0000 (DEVTRAP_EN) pmbase+0x004a: 0x0000 (RESERVED) pmbase+0x004c: 0x00000000 (RESERVED) pmbase+0x0050: 0x00000000 (RESERVED) pmbase+0x0054: 0x00000000 (RESERVED) pmbase+0x0058: 0x00000000 (RESERVED) pmbase+0x005c: 0x00000000 (RESERVED) pmbase+0x0060: 0x27 (TCO_RLD) pmbase+0x0061: 0x32 (TCO_TMR) pmbase+0x0062: 0x00 (TCO_DAT_IN) pmbase+0x0063: 0x00 (TCO_DAT_OUT) pmbase+0x0064: 0x0000 (TCO1_STS) pmbase+0x0066: 0x0000 (TCO2_STS) pmbase+0x0068: 0x0000 (TCO1_CNT) pmbase+0x006a: 0x0008 (TCO2_CNT) pmbase+0x006c: 0x810a (TCO_MESSAGE) pmbase+0x006e: 0x00 (TCO_WDCNT) pmbase+0x006f: 0x00 (RESERVED) pmbase+0x0070: 0x03 (SW_IRQ_GEN) pmbase+0x0071: 0x00 (RESERVED) pmbase+0x0072: 0x0000 (RESERVED) pmbase+0x0074: 0x00000000 (RESERVED) pmbase+0x0078: 0x00000000 (RESERVED) pmbase+0x007c: 0x00000000 (RESERVED)
============= MCHBAR ============
MCHBAR = 0xfecf0000 (MEM)
0x0000: 0x08080804 0x0004: 0x08080808 0x0010: 0x00000011 0x0060: 0x569c0d95 0x0064: 0x001442c6 0x0068: 0x20102271 0x006c: 0x0000d001 0x00b0: 0x00410408 0x00b4: 0x00040830 0x00b8: 0x00040830 0x00bc: 0x00200504 0x0100: 0x0000089b 0x0104: 0x000004ad 0x0130: 0x0000088d 0x0134: 0x00400000 0x0138: 0x4000003c 0x013c: 0x1ff02108 0x0140: 0x0001721c 0x0144: 0x0fff0e38 0x0170: 0x80000000 0x0174: 0x04800052 0x01a0: 0x20000000 0x0200: 0x00000001 0x0208: 0x00004947 0x020c: 0x00005947 0x0300: 0x00000032 0x0800: 0xaaaaaaaa 0x0804: 0xddd888aa 0x0808: 0xdddddddd 0x080c: 0xdddddddd 0x0810: 0xdddddddd 0x0814: 0xdddddddd 0x0818: 0xaa99999d 0x081c: 0xbbbbbbaa 0x0820: 0x0e051000 0x0824: 0x81a90689 0x0828: 0x08001c28 0x082c: 0x00000001 0x0900: 0x0077e000 0x0a00: 0x00000044 0x0a10: 0x00113040 0x0a20: 0x23010203 0x0a24: 0x00003000 0x0a50: 0x0002411a 0x0a54: 0x00426213 0x0b10: 0x9f7fc2b8 0x0b14: 0x00000e0e 0x0b20: 0x0bf56000 0x0b40: 0x84000000 0x0b44: 0x21084210 0x0b48: 0x08421084 0x0b4c: 0x39ce73a3 0x0b50: 0xdef7bdef 0x0b54: 0xf7bdef7b
============= EPBAR =============
This northbrigde does not have EPBAR.
============= DMIBAR ============
This northbrigde does not have DMIBAR.
========= PCIEXBAR ========
This northbrigde does not have PCIEXBAR.
Error: Dumping MSRs on this CPU (0x000f20) is not (yet) supported.
-
Michał Mirosław