r609 - coreboot-v3/mainboard/artecgroup/dbe61

Author: hailfinger
Date: 2008-02-18 18:20:47 +0100 (Mon, 18 Feb 2008)
New Revision: 609

Modified:
   coreboot-v3/mainboard/artecgroup/dbe61/dts
Log:
Modify the artecgroup/dbe61 dts to be equivalent to v2 Config.lb. The 
target does not yet compile due to initram breakage, but the breakage is 
really old.

Signed-off-by: Carl-Daniel Hailfinger 
Acked-by: Marc Jones

Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe61/dts	2008-02-18 16:37:58 UTC (rev 608)
+++ coreboot-v3/mainboard/artecgroup/dbe61/dts	2008-02-18 17:20:47 UTC (rev 609)
@@ -84,8 +84,26 @@
    	pci@1,0 {
    		/config/("northbridge/amd/geodelx/pci");
    	};
-		pci@1,1 {
+		pci@15,0 {
    		/config/("southbridge/amd/cs5536/dts");
+			/* Interrupt enables for LPC bus.
+			 *  Each bit is an IRQ 0-15. */
+			lpc_serirq_enable = "0x00001002";
+			/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
+			lpc_serirq_polarity = "0x0000effd";
+			/* 0:continuous 1:quiet */
+			lpc_serirq_mode = "1";
+			/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. 
+			 * See virtual PIC spec. */
+			enable_gpio_int_route = "0x0D0C0700";
+			/* COM1 settings */
+			com1_enable = "0";
+			com1_address = "0x2f8";
+			com1_irq = "3";
+			/* COM2 settings */
+			com2_enable = "1";
+			com2_address = "0x3f8";
+			com2_irq = "4";
    	};
    };
 };