cs5536: Add a NAND device and do the IDE PCI header disabling on time.
This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better. It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2 before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it enabled in VSA2. It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch, but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the VSA2 bug suggests something further will still need fixing. There are also more potential opportunities to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup actually works right in the current form.
Also corrected the documentation of ide_init() to match current reality.
Signed-off-by: Mart Raudsepp mart.raudsepp@artecdesign.ee --- mainboard/artecgroup/dbe61/dts | 3 ++ mainboard/artecgroup/dbe62/dts | 3 ++ southbridge/amd/cs5536/cs5536.c | 47 ++++++++++++++++++++++++-------------- southbridge/amd/cs5536/nand | 23 +++++++++++++++++++ 4 files changed, 59 insertions(+), 17 deletions(-) create mode 100644 southbridge/amd/cs5536/nand
diff --git a/mainboard/artecgroup/dbe61/dts b/mainboard/artecgroup/dbe61/dts index b443533..48df288 100644 --- a/mainboard/artecgroup/dbe61/dts +++ b/mainboard/artecgroup/dbe61/dts @@ -109,6 +109,9 @@ end /* USB Port Power Handling setting. */ pph = "0xf5"; }; + pci@f,1 { + /config/("southbridge/amd/cs5536/nand"); + }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); }; diff --git a/mainboard/artecgroup/dbe62/dts b/mainboard/artecgroup/dbe62/dts index 213c397..3cbe0ff 100644 --- a/mainboard/artecgroup/dbe62/dts +++ b/mainboard/artecgroup/dbe62/dts @@ -63,6 +63,9 @@ /* USB Port Power Handling setting. */ pph = "0xf5"; }; + pci@f,1 { + /config/("southbridge/amd/cs5536/nand"); + }; pci@f,2 { /config/("southbridge/amd/cs5536/ide"); }; diff --git a/southbridge/amd/cs5536/cs5536.c b/southbridge/amd/cs5536/cs5536.c index 89d64d6..0c5adb1 100644 --- a/southbridge/amd/cs5536/cs5536.c +++ b/southbridge/amd/cs5536/cs5536.c @@ -98,6 +98,21 @@ static void hide_vpci(u32 vpci_devid) }
/** + * Enables the FLASH PCI header when NAND device existing in mainboard device + * tree. Used when the mainboard has a FLASH part instead of an IDE drive and + * that fact is expressed in the mainboard device tree. + * Must be called after VSA init but before PCI scans to enable the flash + * PCI device header early enough - that is .phase2_fixup of the device. + * + * @param dev The device. + */ +static void nand_phase2(struct device *dev) +{ + /* Tell VSA to use FLASH PCI header. Not IDE header. */ + hide_vpci(0x800079C4); +} + +/** * Power button setup. * * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which @@ -170,16 +185,6 @@ static void chipset_flash_setup(struct southbridge_amd_cs5536_dts_config *sb) printk(BIOS_DEBUG, "chipset_flash_setup: Finish\n"); }
-/** - * Use this in the event that you have a FLASH part instead of an IDE drive. - * Run after VSA init to enable the flash PCI device header. - */ -static void enable_ide_nand_flash_header(void) -{ - /* Tell VSA to use FLASH PCI header. Not IDE header. */ - hide_vpci(0x800079C4); -} - #define RTC_CENTURY 0x32 #define RTC_DOMA 0x3D #define RTC_MONA 0x3E @@ -601,8 +606,8 @@ void chipsetinit(void) #define IDE_ETC 0x50
/** - * Enabled the IDE. This is code that is optionally run if the ide_enable is set - * in the mainboard dts. + * Enables the IDE. This is code that is run if there is an ide device in the mainboard + * device tree and it has set non-zero "enable_ide". * * @param dev The device */ @@ -658,11 +663,6 @@ static void southbridge_init(struct device *dev) printk(BIOS_SPEW, "cs5536: done second call vr_write\n"); }
- printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", - __FUNCTION__, sb->enable_ide_nand_flash); - if (sb->enable_ide_nand_flash != 0) - enable_ide_nand_flash_header(); - enable_USB_port4(sb);
/* disable unwanted virtual PCI devices */ @@ -733,3 +733,16 @@ struct device_operations cs5536_ide = { .ops_pci = &pci_dev_ops_pci, };
+struct device_operations cs5536_nand = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_CS5536_FLASH}}}, + .constructor = default_device_constructor, + .phase2_fixup = nand_phase2, + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = 0, /* No Option ROMs */ + .ops_pci = &pci_dev_ops_pci, +}; diff --git a/southbridge/amd/cs5536/nand b/southbridge/amd/cs5536/nand new file mode 100644 index 0000000..69f4fa4 --- /dev/null +++ b/southbridge/amd/cs5536/nand @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Mart Raudsepp mart.raudsepp@artecdesign.ee + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "cs5536_nand"; +};
Mart Raudsepp wrote:
cs5536: Add a NAND device and do the IDE PCI header disabling on time.
This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better. It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2 before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it enabled in VSA2. It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch, but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the VSA2 bug suggests something further will still need fixing. There are also more potential opportunities to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup actually works right in the current form.
Also corrected the documentation of ide_init() to match current reality.
Signed-off-by: Mart Raudsepp mart.raudsepp@artecdesign.ee
Acked-by: Peter Stuge peter@stuge.se
Ühel kenal päeval, R, 2009-01-09 kell 15:29, kirjutas Peter Stuge:
Mart Raudsepp wrote:
cs5536: Add a NAND device and do the IDE PCI header disabling on time.
This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better. It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2 before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it enabled in VSA2. It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch, but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the VSA2 bug suggests something further will still need fixing. There are also more potential opportunities to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup actually works right in the current form.
Also corrected the documentation of ide_init() to match current reality.
Signed-off-by: Mart Raudsepp mart.raudsepp@artecdesign.ee
Acked-by: Peter Stuge peter@stuge.se
Here's a new patch for the same thing. It adds a dev->enabled check to nand_phase2 hide_vpci call compared to the previous, so that it won't switch to NAND if some mainboard dts decides to add a nand device that is spedified to be "disabled;".
Regards, Mart Raudsepp
Mart Raudsepp wrote:
From 21de84bab3d32cefd71a2e95e6caf4f505c4cbff Mon Sep 17 00:00:00 2001 From: Mart Raudsepp mart.raudsepp@artecdesign.ee Date: Thu, 8 Jan 2009 20:49:16 +0200 Subject: [PATCH] cs5536: Add a NAND device and do the IDE PCI header disabling on time.
This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better. It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2 before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it enabled in VSA2. It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch, but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the VSA2 bug suggests something further will still need fixing. There are also more potential opportunities to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup actually works right in the current form.
Also corrected the documentation of ide_init() to match current reality.
Signed-off-by: Mart Raudsepp mart.raudsepp@artecdesign.ee
Acked-by: Peter Stuge peter@stuge.se
peOn Fri, Jan 9, 2009 at 10:40 AM, Peter Stuge peter@stuge.se wrote:
Mart Raudsepp wrote:
From 21de84bab3d32cefd71a2e95e6caf4f505c4cbff Mon Sep 17 00:00:00 2001 From: Mart Raudsepp mart.raudsepp@artecdesign.ee Date: Thu, 8 Jan 2009 20:49:16 +0200 Subject: [PATCH] cs5536: Add a NAND device and do the IDE PCI header disabling on time.
This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better. It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2 before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it enabled in VSA2. It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch, but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the VSA2 bug suggests something further will still need fixing. There are also more potential opportunities to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup actually works right in the current form.
Also corrected the documentation of ide_init() to match current reality.
Signed-off-by: Mart Raudsepp mart.raudsepp@artecdesign.ee
Acked-by: Peter Stuge peter@stuge.se
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Peter already acked but for what it is worth.
Acked-by; Marc Jones marcj303@gmail.com
-----Original Message----- From: coreboot-bounces+mylesgw=gmail.com@coreboot.org [mailto:coreboot- bounces+mylesgw=gmail.com@coreboot.org] On Behalf Of Mart Raudsepp Sent: Friday, January 09, 2009 5:21 AM To: coreboot@coreboot.org Subject: [coreboot] [PATCH 1/2] cs5536: Add a NAND device and do the IDE PCI header disabling on time.
cs5536: Add a NAND device and do the IDE PCI header disabling on time.
This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better. It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2 before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it enabled in VSA2. It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch, but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the VSA2 bug suggests something further will still need fixing. There are also more potential opportunities to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup actually works right in the current form.
Also corrected the documentation of ide_init() to match current reality.
Signed-off-by: Mart Raudsepp mart.raudsepp@artecdesign.ee
mainboard/artecgroup/dbe61/dts | 3 ++ mainboard/artecgroup/dbe62/dts | 3 ++ southbridge/amd/cs5536/cs5536.c | 47 ++++++++++++++++++++++++----------
southbridge/amd/cs5536/nand | 23 +++++++++++++++++++ 4 files changed, 59 insertions(+), 17 deletions(-) create mode 100644 southbridge/amd/cs5536/nand
diff --git a/mainboard/artecgroup/dbe61/dts b/mainboard/artecgroup/dbe61/dts index b443533..48df288 100644 --- a/mainboard/artecgroup/dbe61/dts +++ b/mainboard/artecgroup/dbe61/dts @@ -109,6 +109,9 @@ end /* USB Port Power Handling setting. */ pph = "0xf5"; };
pci@f,1 {/config/("southbridge/amd/cs5536/nand");};
Shouldn't you remove the ide device if it's going to be hidden?
diff --git a/mainboard/artecgroup/dbe62/dts b/mainboard/artecgroup/dbe62/dts index 213c397..3cbe0ff 100644 --- a/mainboard/artecgroup/dbe62/dts +++ b/mainboard/artecgroup/dbe62/dts @@ -63,6 +63,9 @@ /* USB Port Power Handling setting. */ pph = "0xf5"; };
pci@f,1 {/config/("southbridge/amd/cs5536/nand");};
Same thing here.
Maybe it would be better to have IDE/NAND selection depend on a CMOS/NVRAM value, so that the same BIOS could be used with either choice.
Could we make an ide_or_nand device that called your nand_phase2 if it was nand, and used the ide_init if it wasn't. They seem so similar, and only one is allowed at a time.
Thanks, Myles
Myles Watson wrote:
Could we make an ide_or_nand device that called your nand_phase2 if it was nand, and used the ide_init if it wasn't. They seem so similar, and only one is allowed at a time.
I'm not sure I like that because they always have different PCI ids..
//Peter
-----Original Message----- From: coreboot-bounces+mylesgw=gmail.com@coreboot.org [mailto:coreboot- bounces+mylesgw=gmail.com@coreboot.org] On Behalf Of Peter Stuge Sent: Friday, January 09, 2009 7:36 AM To: coreboot@coreboot.org Subject: Re: [coreboot] [PATCH 1/2] cs5536: Add a NAND device and do the IDEPCI header disabling on time.
Myles Watson wrote:
Could we make an ide_or_nand device that called your nand_phase2 if it was nand, and used the ide_init if it wasn't. They seem so similar, and only one is allowed at a time.
I'm not sure I like that because they always have different PCI ids..
Good catch. You're right.
Thanks, Myles
Ühel kenal päeval, R, 2009-01-09 kell 07:33, kirjutas Myles Watson:
-----Original Message----- From: coreboot-bounces+mylesgw=gmail.com@coreboot.org [mailto:coreboot- bounces+mylesgw=gmail.com@coreboot.org] On Behalf Of Mart Raudsepp Sent: Friday, January 09, 2009 5:21 AM To: coreboot@coreboot.org Subject: [coreboot] [PATCH 1/2] cs5536: Add a NAND device and do the IDE PCI header disabling on time.
cs5536: Add a NAND device and do the IDE PCI header disabling on time.
This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better. It allows us to do the IDE PCI header early enough in a clean way - the hide_vpci was called way too late before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2 before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it enabled in VSA2. It makes NAND setup work better, but still not completely. There is a VSA2 bug for which I made a patch, but waiting on a new binary to test if after that everything works or not. A quick hack to workaround the VSA2 bug suggests something further will still need fixing. There are also more potential opportunities to shuffle NAND code around to match v3 approach better, but that's a next step for me after NAND setup actually works right in the current form.
Also corrected the documentation of ide_init() to match current reality.
Signed-off-by: Mart Raudsepp mart.raudsepp@artecdesign.ee
mainboard/artecgroup/dbe61/dts | 3 ++ mainboard/artecgroup/dbe62/dts | 3 ++ southbridge/amd/cs5536/cs5536.c | 47 ++++++++++++++++++++++++----------
southbridge/amd/cs5536/nand | 23 +++++++++++++++++++ 4 files changed, 59 insertions(+), 17 deletions(-) create mode 100644 southbridge/amd/cs5536/nand
diff --git a/mainboard/artecgroup/dbe61/dts b/mainboard/artecgroup/dbe61/dts index b443533..48df288 100644 --- a/mainboard/artecgroup/dbe61/dts +++ b/mainboard/artecgroup/dbe61/dts @@ -109,6 +109,9 @@ end /* USB Port Power Handling setting. */ pph = "0xf5"; };
pci@f,1 {/config/("southbridge/amd/cs5536/nand");};Shouldn't you remove the ide device if it's going to be hidden?
With this patch there is still an enable_ide that has a default of zero via southbridge/amd/cs5536/ide. The 2/2 patch does the enable_ide killing and removal of this entry as you suggest.
diff --git a/mainboard/artecgroup/dbe62/dts b/mainboard/artecgroup/dbe62/dts index 213c397..3cbe0ff 100644 --- a/mainboard/artecgroup/dbe62/dts +++ b/mainboard/artecgroup/dbe62/dts @@ -63,6 +63,9 @@ /* USB Port Power Handling setting. */ pph = "0xf5"; };
pci@f,1 {/config/("southbridge/amd/cs5536/nand");};Same thing here.
And same reply :)
Maybe it would be better to have IDE/NAND selection depend on a CMOS/NVRAM value, so that the same BIOS could be used with either choice.
The board doesn't have IDE stuff wired anywhere. No existing boards supported by coreboot do to my knowledge. I'm thinking that if a board appears that wants to do it, we'd have both devices in the dts and have the mainboard (or NVRAM handler) specific code disable one of them before phase2 of devices with dev_set_enabled(dev, 0)
Could we make an ide_or_nand device that called your nand_phase2 if it was nand, and used the ide_init if it wasn't. They seem so similar, and only one is allowed at a time.
How do we get pci@f,1 in case of Flash and pci@f,2 in case of IDE then if there is an ide_or_nand device?
Mart Raudsepp
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Mart Raudsepp Sent: Friday, January 09, 2009 7:41 AM To: coreboot@coreboot.org Subject: Re: [coreboot] [PATCH 1/2] cs5536: Add a NAND device and do the IDE PCI header disabling on time.
Ühel kenal päeval, R, 2009-01-09 kell 07:33, kirjutas Myles Watson:
-----Original Message----- From: coreboot-bounces+mylesgw=gmail.com@coreboot.org
[mailto:coreboot-
bounces+mylesgw=gmail.com@coreboot.org] On Behalf Of Mart Raudsepp Sent: Friday, January 09, 2009 5:21 AM To: coreboot@coreboot.org Subject: [coreboot] [PATCH 1/2] cs5536: Add a NAND device and do the
IDE
PCI header disabling on time.
cs5536: Add a NAND device and do the IDE PCI header disabling on time.
This implements a nand device, akin to the ide device to follow the coreboot-v3 device tree design better. It allows us to do the IDE PCI header early enough in a clean way -
the
hide_vpci was called way too late before - in phase6 of southbridge device, but we need the Flash header active instead of IDE in the VSA2 before bus scans happen, or the PCI device gets disabled in coreboot understanding by the time we get it enabled in VSA2. It makes NAND setup work better, but still not completely. There is a
VSA2
bug for which I made a patch, but waiting on a new binary to test if after that everything works or
not.
A quick hack to workaround the VSA2 bug suggests something further will still need fixing. There are
also
more potential opportunities to shuffle NAND code around to match v3 approach better, but that's a
next
step for me after NAND setup actually works right in the current form.
Also corrected the documentation of ide_init() to match current
reality.
Signed-off-by: Mart Raudsepp mart.raudsepp@artecdesign.ee
mainboard/artecgroup/dbe61/dts | 3 ++ mainboard/artecgroup/dbe62/dts | 3 ++ southbridge/amd/cs5536/cs5536.c | 47 ++++++++++++++++++++++++------
southbridge/amd/cs5536/nand | 23 +++++++++++++++++++ 4 files changed, 59 insertions(+), 17 deletions(-) create mode 100644 southbridge/amd/cs5536/nand
diff --git a/mainboard/artecgroup/dbe61/dts b/mainboard/artecgroup/dbe61/dts index b443533..48df288 100644 --- a/mainboard/artecgroup/dbe61/dts +++ b/mainboard/artecgroup/dbe61/dts @@ -109,6 +109,9 @@ end /* USB Port Power Handling setting. */ pph = "0xf5"; };
pci@f,1 {/config/("southbridge/amd/cs5536/nand");};Shouldn't you remove the ide device if it's going to be hidden?
With this patch there is still an enable_ide that has a default of zero via southbridge/amd/cs5536/ide. The 2/2 patch does the enable_ide killing and removal of this entry as you suggest.
diff --git a/mainboard/artecgroup/dbe62/dts b/mainboard/artecgroup/dbe62/dts index 213c397..3cbe0ff 100644 --- a/mainboard/artecgroup/dbe62/dts +++ b/mainboard/artecgroup/dbe62/dts @@ -63,6 +63,9 @@ /* USB Port Power Handling setting. */ pph = "0xf5"; };
pci@f,1 {/config/("southbridge/amd/cs5536/nand");};Same thing here.
And same reply :)
Maybe it would be better to have IDE/NAND selection depend on a
CMOS/NVRAM
value, so that the same BIOS could be used with either choice.
The board doesn't have IDE stuff wired anywhere. No existing boards supported by coreboot do to my knowledge. I'm thinking that if a board appears that wants to do it, we'd have both devices in the dts and have the mainboard (or NVRAM handler) specific code disable one of them before phase2 of devices with dev_set_enabled(dev, 0)
That's the answer to the question I should have asked. :) Thanks for the clarification.
Could we make an ide_or_nand device that called your nand_phase2 if it
was
nand, and used the ide_init if it wasn't. They seem so similar, and
only
one is allowed at a time.
How do we get pci@f,1 in case of Flash and pci@f,2 in case of IDE then if there is an ide_or_nand device?
Yes. They were separate suggestions.
Thanks, Myles
Mart Raudsepp wrote:
The board doesn't have IDE stuff wired anywhere. No existing boards supported by coreboot do to my knowledge.
ALIX.1, .2 and .6 boards have the CF on IDE and an IDE header in parallell.
//Peter
Ühel kenal päeval, R, 2009-01-09 kell 15:46, kirjutas Peter Stuge:
Mart Raudsepp wrote:
The board doesn't have IDE stuff wired anywhere. No existing boards supported by coreboot do to my knowledge.
ALIX.1, .2 and .6 boards have the CF on IDE and an IDE header in parallell.
Sorry, I meant that no existing board supported by coreboot has IDE and Flash interface wired at the same time currently.
Does your comment still apply then in relation to enable_ide existence perhaps? How is the selection between CF and IDE header done on those ALIX boards?
Mart Raudsepp
Mart Raudsepp wrote:
Sorry, I meant that no existing board supported by coreboot has IDE and Flash interface wired at the same time currently.
Ah right! No, I haven't seen that. Seems a little unlikely because IDE would be PIO only.
Does your comment still apply then in relation to enable_ide existence perhaps?
Guess not. I think the motivation for enable_ide is simply one of consistency. Most chipsets do not allow the IDE PCI device to be hidden completely so enable_ide was added to control how it gets configured.
How is the selection between CF and IDE header done on those ALIX boards?
They're just parallell, and there's a master/slave jumper for the CF.
//Peter
On Fri, Jan 09, 2009 at 07:33:37AM -0700, Myles Watson wrote:
Maybe it would be better to have IDE/NAND selection depend on a CMOS/NVRAM value, so that the same BIOS could be used with either choice.
Will that work on boards without cmos battery (they exist - alix2c3 for instance)?
Thanks, Ward.
-----Original Message----- From: Ward Vandewege [mailto:ward@gnu.org] Sent: Friday, January 09, 2009 7:46 AM To: Myles Watson Cc: coreboot@coreboot.org Subject: Re: [coreboot] [PATCH 1/2] cs5536: Add a NAND device and do theIDE PCI header disabling on time.
On Fri, Jan 09, 2009 at 07:33:37AM -0700, Myles Watson wrote:
Maybe it would be better to have IDE/NAND selection depend on a
CMOS/NVRAM
value, so that the same BIOS could be used with either choice.
Will that work on boards without cmos battery (they exist - alix2c3 for instance)?
Maybe there are no boards with IDE and NAND support? If there are, are there any without a CMOS battery? How would the factory BIOS handle selection?
I was just brainstorming.
Thanks, Myles
Ühel kenal päeval, R, 2009-01-09 kell 07:55, kirjutas Myles Watson:
-----Original Message----- From: Ward Vandewege [mailto:ward@gnu.org] Sent: Friday, January 09, 2009 7:46 AM To: Myles Watson Cc: coreboot@coreboot.org Subject: Re: [coreboot] [PATCH 1/2] cs5536: Add a NAND device and do theIDE PCI header disabling on time.
On Fri, Jan 09, 2009 at 07:33:37AM -0700, Myles Watson wrote:
Maybe it would be better to have IDE/NAND selection depend on a
CMOS/NVRAM
value, so that the same BIOS could be used with either choice.
Will that work on boards without cmos battery (they exist - alix2c3 for instance)?
Maybe there are no boards with IDE and NAND support? If there are, are there any without a CMOS battery? How would the factory BIOS handle selection?
There's a default CMOS content to fall back to, so during build configuration you'd probably select the default and then in NVRAM be able to switch that around. If there is no CMOS battery or it gets reset (checksums don't validate or so) you just fall back to the fallback iirc. So without a CMOS battery you'd always have the default chosen at build time, but you can switch by booting from the default and changing it with nvramtool and soft restarting without removing power, or with a currently non-existent setup menu payload in the future.
Everything highly hypothetical and if there are no boards with both supported based on this choice, then it's quite unlikely new ones will appear either given the status of GeodeLX.
Regards, Mart Raudsepp
On Fri, Jan 09, 2009 at 05:06:31PM +0200, Mart Raudsepp wrote:
-----Original Message----- From: Ward Vandewege [mailto:ward@gnu.org] Sent: Friday, January 09, 2009 7:46 AM To: Myles Watson Cc: coreboot@coreboot.org Subject: Re: [coreboot] [PATCH 1/2] cs5536: Add a NAND device and do theIDE PCI header disabling on time.
On Fri, Jan 09, 2009 at 07:33:37AM -0700, Myles Watson wrote:
Maybe it would be better to have IDE/NAND selection depend on a
CMOS/NVRAM
value, so that the same BIOS could be used with either choice.
Will that work on boards without cmos battery (they exist - alix2c3 for instance)?
Maybe there are no boards with IDE and NAND support? If there are, are there any without a CMOS battery? How would the factory BIOS handle selection?
There's a default CMOS content to fall back to, so during build configuration you'd probably select the default and then in NVRAM be able to switch that around. If there is no CMOS battery or it gets reset (checksums don't validate or so) you just fall back to the fallback iirc. So without a CMOS battery you'd always have the default chosen at build time, but you can switch by booting from the default and changing it with nvramtool and soft restarting without removing power, or with a currently non-existent setup menu payload in the future.
Everything highly hypothetical and if there are no boards with both supported based on this choice, then it's quite unlikely new ones will appear either given the status of GeodeLX.
Agreed. Sounds good to me.
Thanks, Ward.
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Marc Jones -
Mart Raudsepp -
Myles Watson -
Peter Stuge -
Ward Vandewege