SPIBAR + 0x10 offset with MMIOREAD32 causing exception

[Rao G]

Hi All,

Trying to access SPI Flash from EFI payload

1)
SpiInstance->PchSpiBase = MmPciBase (
                              DEFAULT_PCI_BUS_NUMBER_PCH,
                              PCI_DEVICE_NUMBER_PCH_SPI,
                              PCI_FUNCTION_NUMBER_PCH_SPI
                              );
DEBUG ((DEBUG_INFO, "PchSpiBase at 0x%x\n", SpiInstance->PchSpiBase));
> > returns PchSpiBase as 0xC00FD000 (Bus 0 Dev 1F Func 0)

2)
ScSpiBar0 = MmioRead32 (SpiInstance->PchSpiBase +
PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000;

Expectation:
this should return value at 0xC00FD010

Result
The above code is throwing processor exception

PchSpiBase at 0xC00FD000
!!!! X64 Exception Type - 0E(#PF - Page-Fault)  CPU Apic ID - 00000000 !!!!
ExceptionData - 0000000000000000  I:0 R:0 U:0 W:0 P:0 PK:0 SS:0 SGX:0
RIP  - 00000000771903D0, CS  - 0000000000000038, RFLAGS - 0000000000010046

Any clues whether SPI flash needs to be enabled in descriptor or any straps
by using FIT tool?

Thanks
Rao

[Nico Huber]

Hi Rao,

On 28.01.22 14:30, Rao G wrote:
> ScSpiBar0 = MmioRead32 (SpiInstance->PchSpiBase +
> PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000;
>
> Expectation:
> this should return value at 0xC00FD010
>
> Result
> The above code is throwing processor exception
>
> PchSpiBase at 0xC00FD000
> !!!! X64 Exception Type - 0E(#PF - Page-Fault)  CPU Apic ID - 00000000 !!!!
> ExceptionData - 0000000000000000  I:0 R:0 U:0 W:0 P:0 PK:0 SS:0 SGX:0
> RIP  - 00000000771903D0, CS  - 0000000000000038, RFLAGS - 0000000000010046

this is literally as it says, a page fault. Just like in any other OS
(and wrt. this UEFI is an OS) you have to map physical memory using page
tables before you can access it. There is likely a very simple function
you have to call to turn your physical address into a virtual pointer
that you can use in C. I'm not familiar with UEFI, so can't tell you
what to call. Better ask UEFI developers.
> Any clues whether SPI flash needs to be enabled in descriptor or any straps
> by using FIT tool?

No, this problem is a generic one and far away from your particular
controller. It's not even about hardware (beside that you run it on
a computer ^^).

Nico

[Jeff Daly]

0xFD000 is bdf 0/1f/5, not 0/1f/0
Is your SPI controller at function 5?    That’s where it usually is for Intel SoCs.

From: Rao G 
Sent: Friday, January 28, 2022 8:31 AM
To: coreboot 
Subject: [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing exception

Caution: This is an external email. Please take care when clicking links or opening attachments.

Hi All,

Trying to access SPI Flash from EFI payload

1)
SpiInstance->PchSpiBase = MmPciBase (
                              DEFAULT_PCI_BUS_NUMBER_PCH,
                              PCI_DEVICE_NUMBER_PCH_SPI,
                              PCI_FUNCTION_NUMBER_PCH_SPI
                              );
DEBUG ((DEBUG_INFO, "PchSpiBase at 0x%x\n", SpiInstance->PchSpiBase));
> > returns PchSpiBase as 0xC00FD000 (Bus 0 Dev 1F Func 0)

2)
ScSpiBar0 = MmioRead32 (SpiInstance->PchSpiBase + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000;

Expectation:
this should return value at 0xC00FD010

Result
The above code is throwing processor exception

PchSpiBase at 0xC00FD000
!!!! X64 Exception Type - 0E(#PF - Page-Fault)  CPU Apic ID - 00000000 !!!!
ExceptionData - 0000000000000000  I:0 R:0 U:0 W:0 P:0 PK:0 SS:0 SGX:0
RIP  - 00000000771903D0, CS  - 0000000000000038, RFLAGS - 0000000000010046

Any clues whether SPI flash needs to be enabled in descriptor or any straps by using FIT tool?

Thanks
Rao

[Rao G]

Yes  0xC00FD000 (Bus 0 Dev 1F Func 5) not Func 0

Thanks
Rao

On Fri, Jan 28, 2022 at 3:40 PM Jeff Daly  wrote:
> 0xFD000 is bdf 0/1f/5, not 0/1f/0
>
> Is your SPI controller at function 5?    That’s where it usually is for
> Intel SoCs.
>
> *From:* Rao G 
> *Sent:* Friday, January 28, 2022 8:31 AM
> *To:* coreboot 
> *Subject:* [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing
> exception
>
> *Caution:* This is an external email. Please take care when clicking
> links or opening attachments.
>
> Hi All,
>
> Trying to access SPI Flash from EFI payload
>
> SpiInstance->PchSpiBase = MmPciBase (
>                               DEFAULT_PCI_BUS_NUMBER_PCH,
>                               PCI_DEVICE_NUMBER_PCH_SPI,
>                               PCI_FUNCTION_NUMBER_PCH_SPI
>                               );
>
> DEBUG ((DEBUG_INFO, "PchSpiBase at 0x%x\n", SpiInstance->PchSpiBase));
> > > returns PchSpiBase as 0xC00FD000 (Bus 0 Dev 1F Func 0)
>
> ScSpiBar0 = MmioRead32 (SpiInstance->PchSpiBase +
> PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000;
>
> Expectation:
>
> this should return value at 0xC00FD010
>
> Result
>
> The above code is throwing processor exception
>
> PchSpiBase at 0xC00FD000
> !!!! X64 Exception Type - 0E(#PF - Page-Fault)  CPU Apic ID - 00000000 !!!!
> ExceptionData - 0000000000000000  I:0 R:0 U:0 W:0 P:0 PK:0 SS:0 SGX:0
> RIP  - 00000000771903D0, CS  - 0000000000000038, RFLAGS - 0000000000010046
>
> Any clues whether SPI flash needs to be enabled in descriptor or any
> straps by using FIT tool?
>
> Thanks
>
> Rao

[Jeff Daly]

And your ECAM base address for PCIE is at 0xC0000000 ?

From: Rao G 
Sent: Friday, January 28, 2022 11:21 AM
To: Jeff Daly ; coreboot 
Subject: Re: [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing exception

Caution: This is an external email. Please take care when clicking links or opening attachments.

Yes  0xC00FD000 (Bus 0 Dev 1F Func 5) not Func 0

Thanks
Rao

On Fri, Jan 28, 2022 at 3:40 PM Jeff Daly <[e-mail]> wrote:
0xFD000 is bdf 0/1f/5, not 0/1f/0
Is your SPI controller at function 5?    That’s where it usually is for Intel SoCs.

From: Rao G <[e-mail]>
Sent: Friday, January 28, 2022 8:31 AM
To: coreboot <[e-mail]>
Subject: [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing exception

Caution: This is an external email. Please take care when clicking links or opening attachments.

Hi All,

Trying to access SPI Flash from EFI payload

1)
SpiInstance->PchSpiBase = MmPciBase (
                              DEFAULT_PCI_BUS_NUMBER_PCH,
                              PCI_DEVICE_NUMBER_PCH_SPI,
                              PCI_FUNCTION_NUMBER_PCH_SPI
                              );
DEBUG ((DEBUG_INFO, "PchSpiBase at 0x%x\n", SpiInstance->PchSpiBase));
> > returns PchSpiBase as 0xC00FD000 (Bus 0 Dev 1F Func 0)

2)
ScSpiBar0 = MmioRead32 (SpiInstance->PchSpiBase + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000;

Expectation:
this should return value at 0xC00FD010

Result
The above code is throwing processor exception

PchSpiBase at 0xC00FD000
!!!! X64 Exception Type - 0E(#PF - Page-Fault)  CPU Apic ID - 00000000 !!!!
ExceptionData - 0000000000000000  I:0 R:0 U:0 W:0 P:0 PK:0 SS:0 SGX:0
RIP  - 00000000771903D0, CS  - 0000000000000038, RFLAGS - 0000000000010046

Any clues whether SPI flash needs to be enabled in descriptor or any straps by using FIT tool?

Thanks
Rao

[Rao G]

That's correct, PCIE_BASE                    = 0xC0000000

On Fri, Jan 28, 2022 at 4:32 PM Jeff Daly  wrote:
> And your ECAM base address for PCIE is at 0xC0000000 ?
>
> *From:* Rao G 
> *Sent:* Friday, January 28, 2022 11:21 AM
> *To:* Jeff Daly ; coreboot 
> *Subject:* Re: [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing
> exception
>
> *Caution:* This is an external email. Please take care when clicking
> links or opening attachments.
>
> Yes  0xC00FD000 (Bus 0 Dev 1F Func 5) not Func 0
>
> Thanks
>
> Rao
>
> On Fri, Jan 28, 2022 at 3:40 PM Jeff Daly  wrote:
>
> 0xFD000 is bdf 0/1f/5, not 0/1f/0
>
> Is your SPI controller at function 5?    That’s where it usually is for
> Intel SoCs.
>
> *From:* Rao G 
> *Sent:* Friday, January 28, 2022 8:31 AM
> *To:* coreboot 
> *Subject:* [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing
> exception
>
> *Caution:* This is an external email. Please take care when clicking
> links or opening attachments.
>
> Hi All,
>
> Trying to access SPI Flash from EFI payload
>
> SpiInstance->PchSpiBase = MmPciBase (
>                               DEFAULT_PCI_BUS_NUMBER_PCH,
>                               PCI_DEVICE_NUMBER_PCH_SPI,
>                               PCI_FUNCTION_NUMBER_PCH_SPI
>                               );
>
> DEBUG ((DEBUG_INFO, "PchSpiBase at 0x%x\n", SpiInstance->PchSpiBase));
> > > returns PchSpiBase as 0xC00FD000 (Bus 0 Dev 1F Func 0)
>
> ScSpiBar0 = MmioRead32 (SpiInstance->PchSpiBase +
> PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000;
>
> Expectation:
>
> this should return value at 0xC00FD010
>
> Result
>
> The above code is throwing processor exception
>
> PchSpiBase at 0xC00FD000
> !!!! X64 Exception Type - 0E(#PF - Page-Fault)  CPU Apic ID - 00000000 !!!!
> ExceptionData - 0000000000000000  I:0 R:0 U:0 W:0 P:0 PK:0 SS:0 SGX:0
> RIP  - 00000000771903D0, CS  - 0000000000000038, RFLAGS - 0000000000010046
>
> Any clues whether SPI flash needs to be enabled in descriptor or any
> straps by using FIT tool?
>
> Thanks
>
> Rao

[Jeff Daly]

What platform are we talking about here, and are you sure this isn’t a bit of hardware that hasn’t been disabled during boot somehow?

From: Rao G 
Sent: Friday, January 28, 2022 11:55 AM
To: Jeff Daly 
Cc: coreboot 
Subject: Re: [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing exception

Caution: This is an external email. Please take care when clicking links or opening attachments.

That's correct, PCIE_BASE                    = 0xC0000000

On Fri, Jan 28, 2022 at 4:32 PM Jeff Daly <[e-mail]> wrote:
And your ECAM base address for PCIE is at 0xC0000000 ?

From: Rao G <[e-mail]>
Sent: Friday, January 28, 2022 11:21 AM
To: Jeff Daly <[e-mail]>; coreboot <[e-mail]>
Subject: Re: [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing exception

Caution: This is an external email. Please take care when clicking links or opening attachments.

Yes  0xC00FD000 (Bus 0 Dev 1F Func 5) not Func 0

Thanks
Rao

On Fri, Jan 28, 2022 at 3:40 PM Jeff Daly <[e-mail]> wrote:
0xFD000 is bdf 0/1f/5, not 0/1f/0
Is your SPI controller at function 5?    That’s where it usually is for Intel SoCs.

From: Rao G <[e-mail]>
Sent: Friday, January 28, 2022 8:31 AM
To: coreboot <[e-mail]>
Subject: [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing exception

Caution: This is an external email. Please take care when clicking links or opening attachments.

Hi All,

Trying to access SPI Flash from EFI payload

1)
SpiInstance->PchSpiBase = MmPciBase (
                              DEFAULT_PCI_BUS_NUMBER_PCH,
                              PCI_DEVICE_NUMBER_PCH_SPI,
                              PCI_FUNCTION_NUMBER_PCH_SPI
                              );
DEBUG ((DEBUG_INFO, "PchSpiBase at 0x%x\n", SpiInstance->PchSpiBase));
> > returns PchSpiBase as 0xC00FD000 (Bus 0 Dev 1F Func 0)

2)
ScSpiBar0 = MmioRead32 (SpiInstance->PchSpiBase + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000;

Expectation:
this should return value at 0xC00FD010

Result
The above code is throwing processor exception

PchSpiBase at 0xC00FD000
!!!! X64 Exception Type - 0E(#PF - Page-Fault)  CPU Apic ID - 00000000 !!!!
ExceptionData - 0000000000000000  I:0 R:0 U:0 W:0 P:0 PK:0 SS:0 SGX:0
RIP  - 00000000771903D0, CS  - 0000000000000038, RFLAGS - 0000000000010046

Any clues whether SPI flash needs to be enabled in descriptor or any straps by using FIT tool?

Thanks
Rao

[Rao G]

This platform is elkhart lake, 32MB SPI flash with coreboot BIOS+EFI Payload

Thanks
Rao

On Fri, Jan 28, 2022 at 5:16 PM Jeff Daly  wrote:
> What platform are we talking about here, and are you sure this isn’t a bit
> of hardware that hasn’t been disabled during boot somehow?
>
> *From:* Rao G 
> *Sent:* Friday, January 28, 2022 11:55 AM
> *To:* Jeff Daly 
> *Cc:* coreboot 
> *Subject:* Re: [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing
> exception
>
> *Caution:* This is an external email. Please take care when clicking
> links or opening attachments.
>
> That's correct, PCIE_BASE                    = 0xC0000000
>
> On Fri, Jan 28, 2022 at 4:32 PM Jeff Daly  wrote:
>
> And your ECAM base address for PCIE is at 0xC0000000 ?
>
> *From:* Rao G 
> *Sent:* Friday, January 28, 2022 11:21 AM
> *To:* Jeff Daly ; coreboot 
> *Subject:* Re: [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing
> exception
>
> *Caution:* This is an external email. Please take care when clicking
> links or opening attachments.
>
> Yes  0xC00FD000 (Bus 0 Dev 1F Func 5) not Func 0
>
> Thanks
>
> Rao
>
> On Fri, Jan 28, 2022 at 3:40 PM Jeff Daly  wrote:
>
> 0xFD000 is bdf 0/1f/5, not 0/1f/0
>
> Is your SPI controller at function 5?    That’s where it usually is for
> Intel SoCs.
>
> *From:* Rao G 
> *Sent:* Friday, January 28, 2022 8:31 AM
> *To:* coreboot 
> *Subject:* [coreboot] SPIBAR + 0x10 offset with MMIOREAD32 causing
> exception
>
> *Caution:* This is an external email. Please take care when clicking
> links or opening attachments.
>
> Hi All,
>
> Trying to access SPI Flash from EFI payload
>
> SpiInstance->PchSpiBase = MmPciBase (
>                               DEFAULT_PCI_BUS_NUMBER_PCH,
>                               PCI_DEVICE_NUMBER_PCH_SPI,
>                               PCI_FUNCTION_NUMBER_PCH_SPI
>                               );
>
> DEBUG ((DEBUG_INFO, "PchSpiBase at 0x%x\n", SpiInstance->PchSpiBase));
> > > returns PchSpiBase as 0xC00FD000 (Bus 0 Dev 1F Func 0)
>
> ScSpiBar0 = MmioRead32 (SpiInstance->PchSpiBase +
> PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000;
>
> Expectation:
>
> this should return value at 0xC00FD010
>
> Result
>
> The above code is throwing processor exception
>
> PchSpiBase at 0xC00FD000
> !!!! X64 Exception Type - 0E(#PF - Page-Fault)  CPU Apic ID - 00000000 !!!!
> ExceptionData - 0000000000000000  I:0 R:0 U:0 W:0 P:0 PK:0 SS:0 SGX:0
> RIP  - 00000000771903D0, CS  - 0000000000000038, RFLAGS - 0000000000010046
>
> Any clues whether SPI flash needs to be enabled in descriptor or any
> straps by using FIT tool?
>
> Thanks
>
> Rao