I've been trying for days to get this chipset to pass a ram test, and nothing seems to work. So far, I've tried programming the registers in the order they're programmed in v1, both from raminit.inc and raminitspd.inc. I'm assuming that since there _IS_ a raminit using spd, that the raminit without spd works, or did work at some point. Is that a valid assumption, or should I be starting from scratch? In the comments, there are also notes about register orders that were tried, and notes when it failed, but doesn't say that it ever worked. I've also tried using the ordering from vt8601, which seems to be very similar.
I've been using values from LBv1, values from my lspci, and values that I've come up with from the datasheets. The ram seems to be initializing (checking 16mb takes roughly 20 minutes), but it never passes. Depending on what I use, it either spurts out random values, 0xffffffff, or alternates between that and 0xffffff80. I've also tried it both with the dimm writes in vt8601 and vt694 from v1 and without.
I've also noticed something a bit weird. Rx78[0] controls CKE, and setting it to 1 enables it, according to the docs. lspci reports that it's set to 0, I might be wrong but that doesn't seem quite right. Should I be trusting lspci, and disabling CKE, or writing that off as an error on lspci's part?
Thanks, Corey
On Fri, Mar 16, 2007 at 01:44:08AM -0400, Corey Osgood wrote:
I've been trying for days to get this chipset to pass a ram test, and nothing seems to work. So far, I've tried programming the registers in the order they're programmed in v1, both from raminit.inc and raminitspd.inc. I'm assuming that since there _IS_ a raminit using spd, that the raminit without spd works, or did work at some point. Is that a valid assumption, or should I be starting from scratch? In the comments, there are also notes about register orders that were tried, and notes when it failed, but doesn't say that it ever worked. I've also tried using the ordering from vt8601, which seems to be very similar.
I don't know whether the v1 code is supposed to work, but there's a commit message of "Works on more memory with this settings" so I guess it should work...
Maybe we should just give it a try? I'll see if I can successfully compile the v1 code...
I've been using values from LBv1, values from my lspci, and values that I've come up with from the datasheets. The ram seems to be initializing (checking 16mb takes roughly 20 minutes),
20 minutes? That sounds pretty long. With the 440BX northbridge it takes a few seconds at most (but doesn't work either ;)
but it never passes. Depending on what I use, it either spurts out random values, 0xffffffff, or alternates between that and 0xffffff80.
FWIW, that's the same behaviour I see with the (non-working) 440BX code... I guess if we find the solution for one of them, we'll soon be able to support both chipsets...
I've also noticed something a bit weird. Rx78[0] controls CKE, and setting it to 1 enables it, according to the docs. lspci reports that it's set to 0, I might be wrong but that doesn't seem quite right. Should I be trusting lspci, and disabling CKE, or writing that off as an error on lspci's part?
Not sure. But it could be the case that some registers only temporarily have a certain value, but after a successful init/boot the value changes. So lcpci is probably not always the correct thing...
(but please someone correct me if I'm wrong)
Uwe.
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Corey Osgood -
Uwe Hermann