See patch
Am Mittwoch, den 22.04.2009, 09:53 +0200 schrieb Stefan Reinauer:
See patch
Acked-by: Patrick Georgi patrick.georgi@coresystems.de
On 22.04.2009 10:06 Uhr, Patrick Georgi wrote:
Am Mittwoch, den 22.04.2009, 09:53 +0200 schrieb Stefan Reinauer:
See patch
Acked-by: Patrick Georgi patrick.georgi@coresystems.de
r4167
Stefan Reinauer wrote:
+++ src/arch/i386/boot/acpi.c (.../trunk/coreboot-v2)
..
+#if 0 +#if MEM_TRAIN_SEQ != 0
- #error "So far it works on AMD and MEM_TRAIN_SEQ == 0"
+#endif
+#if _RAMBASE < 0x1F00000
- #error "For ACPI RESUME you need to have _RAMBASE at least 31MB"
- #error "Chipset support (S3_NVRAM_EARLY and ACPI_IS_WAKEUP_EARLY functions and memory ctrl)"
- #error "And coreboot memory reserved in mainboard.c"
+#endif +#endif
Why disable these build time checks?
//Peter
On 22.04.2009 18:00 Uhr, Peter Stuge wrote:
Stefan Reinauer wrote:
+++ src/arch/i386/boot/acpi.c (.../trunk/coreboot-v2)
..
+#if 0 +#if MEM_TRAIN_SEQ != 0
- #error "So far it works on AMD and MEM_TRAIN_SEQ == 0"
+#endif
+#if _RAMBASE < 0x1F00000
- #error "For ACPI RESUME you need to have _RAMBASE at least 31MB"
- #error "Chipset support (S3_NVRAM_EARLY and ACPI_IS_WAKEUP_EARLY functions and memory ctrl)"
- #error "And coreboot memory reserved in mainboard.c"
+#endif +#endif
Why disable these build time checks?
//Peter
Because they don't belong in i386 generic code either.. They're mainboard or chipset or CPU specific limitations. Many chipsets have no variable named MEM_TRAIN_SEQ
Stefan
On 22.04.2009 18:30 Uhr, Stefan Reinauer wrote:
On 22.04.2009 18:00 Uhr, Peter Stuge wrote:
+#if MEM_TRAIN_SEQ != 0
- #error "So far it works on AMD and MEM_TRAIN_SEQ == 0"
+#endif
+#if _RAMBASE < 0x1F00000
- #error "For ACPI RESUME you need to have _RAMBASE at least 31MB"
- #error "Chipset support (S3_NVRAM_EARLY and ACPI_IS_WAKEUP_EARLY functions and memory ctrl)"
- #error "And coreboot memory reserved in mainboard.c"
+#endif +#endif
+#if 0
Why disable these build time checks?
//Peter
Because they don't belong in i386 generic code either.. They're mainboard or chipset or CPU specific limitations. Many chipsets have no variable named MEM_TRAIN_SEQ
For a better explanation: The code should go away or go to the right place. I have a lot less bellyache if they're in arch/i386/boot/acpi but that's not their final location. Maybe the checks should go away completely. Or to the AMD northbridge directory?
But before I deleted it, I left it in, commented out. One thing for sure, their place is NOT hardwaremain.c