Re: [coreboot] Flashrom support for EPIA-N(L) - patch for review

[Luc Verhaegen]

On Wed, Jun 17, 2009 at 12:36:41PM +0100, Harrison, Jon (SELEX GALILEO, UK) wrote:
> Hi Guys,
>
> See below patch for flashrom to add support for EPIA-N(L) Programming.
>
> This has been built against R599 and tested for read, write and verify
> on an EPIA-NL 800
>
> Seems to work for me!
>
> Regards,
> Jon
> Index: util/flashrom/board_enable.c
>
> --- util/flashrom/board_enable.c	(revision 599)
> +++ util/flashrom/board_enable.c	(working copy)
> @@ -270,6 +270,44 @@
>  }
>
> /**
> Suited for VIAs EPIA N & NL.
> */
>
> +static int board_via_epia_n(const char *name)
> +{
> struct pci_dev *dev;
> uint16_t base;
> uint8_t val;
> dev = pci_dev_find(0x1106, 0x3227);	/* VT8237R ISA bridge */
> if (!dev) {
> fprintf(stderr, "\nERROR: VT8237R ISA bridge not
>
> found.\n");
> return -1;
> }
> /* All memory cycles, not just ROM ones, go to LPC */
> val = pci_read_byte(dev, 0x59);
> val &= ~0x80;
> pci_write_byte(dev, 0x59, val);
> /* GPIO9 -> output */
> val = pci_read_byte(dev, 0xE4);
> //printf("GPO Pin Select Reg = 0x%02X\n", val);
> val |= 0x20;
> pci_write_byte(dev, 0xE4, val);
> /* Get Power Management IO address. */
> base = pci_read_word(dev, 0x88) & 0xFF80;
> /* Enable GPIO9 which is connected to write protect. */
> val = INB(base + 0x4D);
> //printf("PMM GPIO = 0x%02X\n", val);
> val |= 0x02;
> OUTB(val, base + 0x4D);
> return 0;
>
> +}

Please use
    vt823x_set_all_writes_to_lpc
and
    vt823x_gpio_set

I will verify and fix gpio_set for setting other gpio lines than 12-15, 
in the next hour or so.

Remove the //printf.
> {0x1106, 0x0259, 0x1106, 0xaa08,  0x1106, 0x3227, 0x1106,
>
> 0xAA08, "via",        "epia-n",      "VIA",         "EPIA-N/NL",
> board_via_epia_n},

Please remove the coreboot ids. This hardware can be autodetected, and 
you should not disable rom access in your upcoming coreboot support, and 
therefor will not need this board enable.

So NACK on this first pass, but will ack once issues are addressed, and 
once vt823x_gpio_set is fixed.

Luc Verhaegen.

Flashrom support for EPIA-N(L) - patch for review

[Uwe Hermann]

Hi,

On Thu, Jun 18, 2009 at 12:40:39AM +0200, Luc Verhaegen wrote:
> > See below patch for flashrom to add support for EPIA-N(L) Programming.
> >
> > This has been built against R599 and tested for read, write and verify
> > on an EPIA-NL 800

Nice, thanks!
> > Index: util/flashrom/board_enable.c
> >
> > --- util/flashrom/board_enable.c	(revision 599)
> > +++ util/flashrom/board_enable.c	(working copy)
> > @@ -270,6 +270,44 @@
> >  }
> >
> > /**
> > Suited for VIAs EPIA N & NL.
> > */
> >
> > +static int board_via_epia_n(const char *name)
> > +{
> > struct pci_dev *dev;
> > uint16_t base;
> > uint8_t val;
> > dev = pci_dev_find(0x1106, 0x3227);	/* VT8237R ISA bridge */
> > if (!dev) {
> > fprintf(stderr, "\nERROR: VT8237R ISA bridge not
> >
> > found.\n");
> > return -1;
> > }
> > /* All memory cycles, not just ROM ones, go to LPC */
> > val = pci_read_byte(dev, 0x59);
> > val &= ~0x80;
> > pci_write_byte(dev, 0x59, val);
> > /* GPIO9 -> output */
> > val = pci_read_byte(dev, 0xE4);
> > //printf("GPO Pin Select Reg = 0x%02X\n", val);
> > val |= 0x20;
> > pci_write_byte(dev, 0xE4, val);
> > /* Get Power Management IO address. */
> > base = pci_read_word(dev, 0x88) & 0xFF80;
> > /* Enable GPIO9 which is connected to write protect. */
> > val = INB(base + 0x4D);
> > //printf("PMM GPIO = 0x%02X\n", val);
> > val |= 0x02;
> > OUTB(val, base + 0x4D);
> > return 0;
> >
> > +}
>
> Please use
>    vt823x_set_all_writes_to_lpc
> and
>    vt823x_gpio_set

Yep.

Also, please add a Signed-off-by to all the patches you submit,
see http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure

Thanks, Uwe.

Flashrom support for EPIA-N(L) - patch for review

[Harrison, Jon (SELEX GALILEO, UK)]

Luc,

OK. I'll need to patch vt823x_gpio_set as it doesn't currently support
GPIO < 12.

Jon

-----Original Message-----
From: Luc Verhaegen [mailto:[e-mail]] 
Sent: 17 June 2009 23:41
To: Harrison, Jon (SELEX GALILEO, UK)
Cc: [e-mail]
Subject: Re: [coreboot] Flashrom support for EPIA-N(L) - patch for
review

Please use
    vt823x_set_all_writes_to_lpc
and
    vt823x_gpio_set

I will verify and fix gpio_set for setting other gpio lines than 12-15, 
in the next hour or so.

Remove the //printf.
> {0x1106, 0x0259, 0x1106, 0xaa08,  0x1106, 0x3227, 0x1106,
>
> 0xAA08, "via",        "epia-n",      "VIA",         "EPIA-N/NL",
> board_via_epia_n},

Please remove the coreboot ids. This hardware can be autodetected, and 
you should not disable rom access in your upcoming coreboot support, and

therefor will not need this board enable.

So NACK on this first pass, but will ack once issues are addressed, and 
once vt823x_gpio_set is fixed.

Luc Verhaegen.

SELEX Sensors and Airborne Systems Limited
Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL
A company registered in England & Wales.  Company no. 02426132
********************************************************************
This email and any attachments are confidential to the intended
recipient and may also be privileged. If you are not the intended
recipient please delete it from your system and notify the sender.
You should not copy it or use it for any purpose nor disclose or
distribute its contents to any other person.
********************************************************************

Flashrom support for EPIA-N(L) - patch for review

[Harrison, Jon (SELEX GALILEO, UK)]

Luc,

I've incorporated mods as suggested except for removing the coreboot ids
and updated for r602.

Re-tested erase, read, verify, write, read, verify.

Auto detection doesn't seem to be working properly and at this stage I'm
breaking things so much that the -m switch is necessary for reliable
operation.

Hope this is acceptable.

Regards,
Jon

Patch follows::

Index: board_enable.c
===================================================================
--- board_enable.c	(revision 602)
+++ board_enable.c	(working copy)
@@ -181,18 +181,27 @@
 {
    uint16_t base;
    uint8_t val, bit;
-
-	if ((gpio < 12) || (gpio > 15)) {
+	
+	if ((gpio >= 12) && (gpio <= 15)) {
+		/* GPIO12-15 -> output */
+		val = pci_read_byte(dev, 0xE4);
+		val |= 0x10;
+		pci_write_byte(dev, 0xE4, val);
+	}
+	else if (gpio == 9) {
+		/* GPIO9 -> Output */
+		val = pci_read_byte(dev, 0xE4);
+		val |= 0x20;
+		pci_write_byte(dev, 0xE4, val);
+		
+	}
+	else
+	{
    	fprintf(stderr, "\nERROR: "
    		"VT823x GPIO%02d is not implemented.\n", gpio);
    	return;
    }

-	/* GPIO12-15 -> output */
-	val = pci_read_byte(dev, 0xE4);
-	val |= 0x10;
-	pci_write_byte(dev, 0xE4, val);
-
    /* Now raise/drop the GPIO line itself. */
    bit = 0x01 << (gpio - 8);

@@ -270,6 +279,28 @@
 }

/**
+ * Suited for VIAs EPIA N & NL.
+ */
+static int board_via_epia_n(const char *name)
+{
+	struct pci_dev *dev;
+
+	dev = pci_dev_find(0x1106, 0x3227);	/* VT8237R ISA bridge */
+	if (!dev) {
+		fprintf(stderr, "\nERROR: VT8237R ISA bridge not
found.\n");
+		return -1;
+	}
+
+	/* All memory cycles, not just ROM ones, go to LPC */
+	vt823x_set_all_writes_to_lpc(dev);
+	
+	/* GPIO9 -> output */
+	vt823x_gpio_set(dev, 9, 1);
+
+	return 0;
+}
+
+/**
  * Suited for EPoX EP-8K5A2 and Albatron PM266A.
  */
 static int board_epox_ep_8k5a2(const char *name)
@@ -752,6 +783,7 @@
    {0x1106, 0x0314, 0x1106, 0xaa08,  0x1106, 0x3227, 0x1106,
0xAA08, NULL,         NULL,          "VIA",         "EPIA-CN",
board_via_epia_sp},
    {0x1106, 0x3177, 0x1106, 0xAA01,  0x1106, 0x3123, 0x1106,
0xAA01, NULL,         NULL,          "VIA",         "EPIA M/MII/...",
board_via_epia_m},
    {0x1106, 0x3227, 0x1106, 0xAA01,  0x1106, 0x0259, 0x1106,
0xAA01, NULL,         NULL,          "VIA",         "EPIA SP",
board_via_epia_sp},
+	{0x1106, 0x0259, 0x1106, 0x3227,  0x1106, 0x3065, 0x1106,
0x3149, "via",        "epia-n",      "VIA",         "EPIA-N/NL",
board_via_epia_n},
    {0x1106, 0x5337, 0x1458, 0xb003,  0x1106, 0x287e, 0x1106,
0x337e, "via",        "pc3500g",     "VIA",         "PC3500G",
it87xx_probe_spi_flash},
    {     0,      0,      0,      0,       0,      0,      0,
0, NULL,         NULL,          NULL,          NULL,
NULL}, /* end marker */
 };

-----Original Message-----
From: Luc Verhaegen [mailto:[e-mail]] 
Sent: 17 June 2009 23:41
To: Harrison, Jon (SELEX GALILEO, UK)
Cc: [e-mail]
Subject: Re: [coreboot] Flashrom support for EPIA-N(L) - patch for
review

[snip]

Please use
    vt823x_set_all_writes_to_lpc
and
    vt823x_gpio_set

I will verify and fix gpio_set for setting other gpio lines than 12-15, 
in the next hour or so.

Remove the //printf.
> {0x1106, 0x0259, 0x1106, 0xaa08,  0x1106, 0x3227, 0x1106,
>
> 0xAA08, "via",        "epia-n",      "VIA",         "EPIA-N/NL",
> board_via_epia_n},

Please remove the coreboot ids. This hardware can be autodetected, and 
you should not disable rom access in your upcoming coreboot support, and

therefor will not need this board enable.

So NACK on this first pass, but will ack once issues are addressed, and 
once vt823x_gpio_set is fixed.

Luc Verhaegen.

SELEX Sensors and Airborne Systems Limited
Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL
A company registered in England & Wales.  Company no. 02426132
********************************************************************
This email and any attachments are confidential to the intended
recipient and may also be privileged. If you are not the intended
recipient please delete it from your system and notify the sender.
You should not copy it or use it for any purpose nor disclose or
distribute its contents to any other person.
********************************************************************