FID/VID change and display flicker

[Rudolf Marek]

Hi all,

I finally moved my desktop to the Asrock socket 939 board with 785G/SB700 + 
coreboot. So far even with 6 harddrives and 2GB RAM everything works :)

I only noticed a flicker if CPU freq/voltage changes. I briefly chekced the 
LDTSTOP settings in SB and also in HTIU in NB so far it makes sense. Is it a bug 
or feature? I admit I did not check with original BIOS.

Thanks
Rudolf

Quoting Rudolf Marek :

Hello Rudolf
> I only noticed a flicker if CPU freq/voltage changes.

Are you using the on-board video and have you 2 or more screens connected?

Regards
Christian

[Rudolf Marek]

> Are you using the on-board video and have you 2 or more screens

connected?

Hi,

Yes it is onboard but only one DVI (no dualhead) circa 1920x1200

Thanks
Rudolf

[Rudolf Marek]

Hi all,

I still got the flicker. I checked so far:

PMM settings in the CPU.
LDTSTOP length is SB
HTIU settings with regards of FID/VID change and ALLOW_LDTSTOP
Settings fro the VGA BIOS.

I found in RPR 880 guide (46141_rs880_rpr_pub_3.00.pdf)

8.8.3 ATIVumaSysInfoRev3 Programming
       The system BIOS is responsible for filling in the ATIVumaSysInfoRev3 
table when the video BIOS calls GetIntegratedSystemInformation via INT 15h. The 
table parameters are used by the video BIOS and the video driver to support the 
"C1e/C3/Stutter Mode" feature and the "PowerNow!/Cool'nQuiet" feature. This 
section explains how to program the table entries k8SyncStartDly and k8DataRetTime.

This seems wrong to me, I'm not aware of any 15h interface. Everything is 
handled through the ATOM BIOS in gfx.c where those values seems hardcoded.

Does the 15h interface exists? Or the documentation is wrong?

The HTIU settings:

42dfa202 is coreboot HTIU 0x6
071081c9 is coreboot HTIU 0x7

I'm bit confused that HTIU 7 bits 1 and 2 should be 0, but the guide is telling so.

delay_STPCLK_en 1 0x1 Holds off upstream SMC STPCLK for FID message until
                       DISP_ALLOW_LDTSTOP is asserted. During this time,
                       only DISP can issue request.
                         0=Disable
                         1=Enable
delay_FID_en    2 0x1 Holds off upstream SMC FID message until
                       DISP_ALLOW_LDTSTOP is asserted. Note: This bit should
                       always be set to 0.
                         0=Disable

I checked all PMIO settings and PMM settings and still flicker. I checked also 
the PSS object itself, the only difference is is that I use different VID for 
two highest P-states than the asrock bios. Latency settings etc is the same.

I tried even disassembling the ATOM tables and it only differs in 
ulmemoryclock/bootupumaclock which is 0 in orig bios and 16600 in coreboot.

So... Why I still got the flicker? Is there any other HTIU settings I missed? Or 
what else should I check.

Thanks
Rudolf

On 3.10.2011 08:16, Rudolf Marek wrote:
> Hi all,
>
> I finally moved my desktop to the Asrock socket 939 board with 785G/SB700 +
> coreboot. So far even with 6 harddrives and 2GB RAM everything works :)
>
> I only noticed a flicker if CPU freq/voltage changes. I briefly chekced the
> LDTSTOP settings in SB and also in HTIU in NB so far it makes sense. Is it a bug
> or feature? I admit I did not check with original BIOS.
>
> Thanks
> Rudolf