Patch merged into coreboot/master: bd563e6 udelay: add missing bus frequency

the following patch was just integrated into master:
commit bd563e66681569f8b010f43a2289aa9d82537ec3
Author: Sven Schnelle 
Date:   Sun Jun 10 19:03:36 2012 +0200

udelay: add missing bus frequency

commit 5b6404e4195157eac8d97ae5bf30f45612109d57 ("Fix timer frequency
    detection on Sandybridge") reworked the udelay code, but didn't add
    the 333MHz FSB entry used on Model 15 Xeons.

Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6
    Signed-off-by: Sven Schnelle

Build-Tested: build bot (Jenkins) at Sun Jun 10 19:34:46 2012, giving +1
Reviewed-By: Sven Schnelle  at Tue Jun 12 10:01:15 2012, giving +2
See http://review.coreboot.org/1099 for details.

-gerrit