Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "mjones" checked in revision 6408 to the coreboot repository. This caused the following changes:
Change Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode.
In fact I changed coreDelay before deleting the code in fidvid that called it. But there're still a couple of calls from src/northbridge/amd/amdmct/wrappers/mcti_d.c Since the comment encouraged fixing something, I parametrized it with the delay time in microseconds and paranoically tried to avoid an overflow at pathological moments.
Signed-off-by: Xavi Drudis Ferran xdrudis@tinet.cat Acked-by: Marc Jones marcj303@gmail.com
Build Log: Compilation of amd:bimini_fam10 has been fixed Compilation of amd:tilapia_fam10 has been fixed Compilation of gigabyte:ma785gmt has been fixed
If something broke during this checkin please be a pain in mjones's neck until the issue is fixed.
If this issue is not fixed within 24h the revision should be backed out.
Best regards, coreboot automatic build system
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