v2 patch for alix1c

[ron minnich]

This is the MFGPT patch for alix1c on v2.

Signed-off-by: Ronald G. Minnich

Not tested.

Index: src/mainboard/pcengines/alix1c/Config.lb
===================================================================
--- src/mainboard/pcengines/alix1c/Config.lb    (revision 3294)
+++ src/mainboard/pcengines/alix1c/Config.lb    (working copy)
@@ -148,9 +148,9 @@
                        # Invert mask = IRQ 12 and 1 are active high.
Keyboard and Mouse IRQs. OK
                        # How to get these? Boot linux and do this:
                        # rdmsr 0x51400025
-                       register "lpc_serirq_enable" = "0x000010da"
+                       register "lpc_serirq_enable" = "0x0000105A"
                        # rdmsr 0x5140004e -- polairy is high 16 bits
of low 32 bits
-                       register "lpc_serirq_polarity" = "0x0000EF25"
+                       register "lpc_serirq_polarity" = "0x0000EFA5"
                        # mode is high 10 bits (determined from code)
                        register "lpc_serirq_mode" = "1"
                        # Don't yet know how to find this.

[Ward Vandewege]

On Fri, May 09, 2008 at 10:38:34PM -0700, ron minnich wrote:
> This is the MFGPT patch for alix1c on v2.
>
> Signed-off-by: Ronald G. Minnich
>
> Not tested.

I tried testing the alix.1c on v2 yesterday, but I can't seem to build a
working image.

All I get is

DRAM controller init done.

and then nothing on serial. I still see POST code 11 for a few seconds, POST
code 8 for a second, and then POST code zero.

I've tried v2 head and r3079 (which is where we fixed the stack check stuff),
both are the same.

I used the nrv-compressed padded vsa image that buildrom generates for v3
version of the code. I suspect I'm doing something silly here, but the v2
build seems to expect a 36K vsa image.

Ideas on what I'm doing wrong?

Thanks,
Ward.

[ron minnich]

On Sat, May 10, 2008 at 5:21 AM, Ward Vandewege  wrote:
> I used the nrv-compressed padded vsa image that buildrom generates for v3
> version of the code. I suspect I'm doing something silly here, but the v2
> build seems to expect a 36K vsa image.
>
> Ideas on what I'm doing wrong?

try to go back to the 36k image, not the buildrom one, and see what happens?

no serial out at all?

ron

[Ward Vandewege]

On Sat, May 10, 2008 at 08:36:55AM -0700, ron minnich wrote:
> On Sat, May 10, 2008 at 5:21 AM, Ward Vandewege  wrote:
> > I used the nrv-compressed padded vsa image that buildrom generates for v3
> > version of the code. I suspect I'm doing something silly here, but the v2
> > build seems to expect a 36K vsa image.
> >
> > Ideas on what I'm doing wrong?
>
> try to go back to the 36k image, not the buildrom one, and see what happens?

Which image is that? The amd_vsa_lx_1.01.bin file is 56K and change...
> no serial out at all?

Just that one line that it completed RAM init.

Thanks,
Ward.

[Ward Vandewege]

On Sat, May 10, 2008 at 11:46:24AM -0400, Ward Vandewege wrote:
> On Sat, May 10, 2008 at 08:36:55AM -0700, ron minnich wrote:
> > On Sat, May 10, 2008 at 5:21 AM, Ward Vandewege  wrote:
> > > I used the nrv-compressed padded vsa image that buildrom generates for v3
> > > version of the code. I suspect I'm doing something silly here, but the v2
> > > build seems to expect a 36K vsa image.
> > >
> > > Ideas on what I'm doing wrong?
> >
> > try to go back to the 36k image, not the buildrom one, and see what happens?

Same thing apparently. Serial:

DRAM controller init done.

And then nothing.

Same thing with head and r3079.

Thanks,
Ward.