[LinuxBIOS] [PATCH] Add initial serial output for Via vt82c686

[Corey Osgood]

This patch is just for initial serial output for the Via vt82c686(a/b) 
southbridge, no more and no less. SMBus and the rest of the SuperI/O 
functions are yet to be written. I've confirmed that this works on Tyan 
S2507 (vt686b), and it should also work fine on vt686a. This is based 
rather loosely on Uwe's code for the SMSC FDC37M60x.

Signed-off-by: Corey Osgood

[ron minnich]

On 3/9/07, Corey Osgood  wrote:
> This patch is just for initial serial output for the Via vt82c686(a/b)
> southbridge, no more and no less. SMBus and the rest of the SuperI/O
> functions are yet to be written. I've confirmed that this works on Tyan
> S2507 (vt686b), and it should also work fine on vt686a. This is based
> rather loosely on Uwe's code for the SMSC FDC37M60x.
>
> Signed-off-by: Corey Osgood

Acked-by: Ronald G. Minnich

[Uwe Hermann]

Hi,

On Fri, Mar 09, 2007 at 10:44:21PM -0500, Corey Osgood wrote:
> This patch is just for initial serial output for the Via vt82c686(a/b) 
> southbridge, no more and no less. SMBus and the rest of the SuperI/O 
> functions are yet to be written. I've confirmed that this works on Tyan 
> S2507 (vt686b), and it should also work fine on vt686a. This is based 
> rather loosely on Uwe's code for the SMSC FDC37M60x.
>
> Signed-off-by: Corey Osgood

Nice, thanks.

Maybe I can test this in a few days, I currently don't have access to my
mainboards... A code quick review below:
> Index: src/southbridge/via/vt686/Config.lb
>
> --- src/southbridge/via/vt686/Config.lb	(revision 0)
> +++ src/southbridge/via/vt686/Config.lb	(revision 0)

Not sure. I think we usually use the full part names, so this should
probably be src/southbridge/via/vt82686b/?

How different are vt82686b and vt82686a? Should they become two
different directories? If not, how should the directory be called?
vt82686ab, or just vt82686a and we add a comment that it applies to
the vt82686b as well?

Also, shouldn't all of this go into src/superio/via? AFAIK the
southbridge has a built-in Super I/O, but do we still want to separate
the Super I/O parts and put them in src/superio/via?

Comments anyone?
> @@ -0,0 +1,23 @@
> +##
> +## This file is part of the LinuxBIOS project.
> +##
> +## Copyright (C) 2006 Uwe Hermann

Drop my line, add yourself. This is just a trivial two-line file...
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +##
>
> +config chip.h
> +object superio.o
> Index: src/southbridge/via/vt686/vt686.h
>
> --- src/southbridge/via/vt686/vt686.h	(revision 0)
> +++ src/southbridge/via/vt686/vt686.h	(revision 0)
> @@ -0,0 +1,47 @@
> +/*
> This file is part of the LinuxBIOS project.
> Copyright (C) 2007 Corey Osgood
> This program is free software; you can redistribute it and/or modify
> it under the terms of the GNU General Public License as published by
> the Free Software Foundation; either version 2 of the License, or
> (at your option) any later version.
> This program is distributed in the hope that it will be useful,
> but WITHOUT ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> GNU General Public License for more details.
> You should have received a copy of the GNU General Public License
> along with this program; if not, write to the Free Software
> Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> */
>
> +/* Datasheets:
> VT82C686B: http://www.datasheet4u.com/html/V/T/8/VT82C686B_VIA.pdf.html */

Please also add the exact name and order number (if available) of the datasheet.
See src/northbridge/intel/i440bx/i440bx.h for an example.
> +/* SuperI/0 Configuration Registers */
> +/* Any registers not listed here are for floppy control or are reserved */
> +#define VT686_CFG_PORT	0x3f0

All variables should probably be also called VT82C686A_FOO, etc...
> +#define	VT686_FS	0xE2 /* Function Select */
> +#define	VT686_PP_BA	0xE6 /* Parallel Port Base Addr. (def = 378-F) */
> +#define	VT686_COM1_BA	0xE7 /* Serial Port 1 Base Addr. (def =	3F8-F) */
> +#define	VT686_COM2_BA	0xE8 /* Serial Port 2 Base Addr. (def =	2F8-F) */
> +#define	VT686_COM_CFG	0xEE /* Serial Port Configuration */
> +#define	VT686_POWER	0xEF /* Power Down Control */
> +#define	VT686_PPCTRL	0xF0 /* Parallel Port Control */
> +#define	VT686_SPCTRL	0xF1 /* Serial Port Control */
> +#define	VT686_GP_IO	0xFC /* General Purpose I/O */

GP_IO -> GPIO
> +/* For reference, used PCI IDs and their names in pci_ids.h */
> +/*
> +PCI_VENDOR_ID_VIA		0x1106
> +PCI_DEVICE_ID_VIA_82C686	0x0686 //Function 0, PCI Config
> +PCI_DEVICE_ID_VIA_82C586_1	0x0571 //Function 1, IDE Controller
> +PCI_DEVICE_ID_VIA_82C586_2	0x3038 //Functions 2 & 3, USB Ports 0-1 & 2-3 Config
> +PCI_DEVICE_ID_VIA_82C586_3	0x3040 //Possible 2nd USB Controller? Check lspci, vt686 datasheet doesn't reference
> +PCI_DEVICE_ID_VIA_82C686_4	0x3057 //Function 4, Power Management
> +PCI_DEVICE_ID_VIA_82C686_5	0x3058 //Function 5 AC'97 Codec
> +PCI_DEVICE_ID_VIA_82C686_6	0x3068 //Function 6 MC'97 Codec */
> Index: src/southbridge/via/vt686/vt686_early_serial.c
> ===================================================================
> --- src/southbridge/via/vt686/vt686_early_serial.c	(revision 0)
> +++ src/southbridge/via/vt686/vt686_early_serial.c	(revision 0)
> @@ -0,0 +1,84 @@
> +/*
> This file is part of the LinuxBIOS project.
> Copyright (C) 2006 Uwe Hermann
> Copyright (C) 2007 Corey Osgood
> This program is free software; you can redistribute it and/or modify
> it under the terms of the GNU General Public License as published by
> the Free Software Foundation; either version 2 of the License, or
> (at your option) any later version.
> This program is distributed in the hope that it will be useful,
> but WITHOUT ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> GNU General Public License for more details.
> You should have received a copy of the GNU General Public License
> along with this program; if not, write to the Free Software
> Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> */
>
> +/* This has been ported to the Via vt82c686(a/b) from SMSC FDC37M60x by Corey Osgood */
> +/* See vt686.h FMI */

For more information? Write the full text, no need to obfuscate.
> +#include <arch/romcc_io.h>
> +#include <device/pci_ids.h>
> +#include "vt686.h"
>
> +#define SIO_BASE			VT686_CFG_PORT
> +#define SIO_INDEX			SIO_BASE
> +#define SIO_DATA			SIO_BASE+1
>
> +static void vt686_sio_write( uint8_t index, uint8_t value )
> +{
> /* 2) Configure the chip */
> /*   a) Write index to port 3F0 */

0x3f0
> outb(index, SIO_BASE);
> /*   b) Read / write data from / to port 3F1 */

0x3f1

This only writes, drop the comment about reads.
> outb(value, SIO_DATA);
> /*   c) Repeat a and b for all desired registers */

You can drop this comment.
> +}
>
> +/* Enable the peripheral devices on the VT686 Super I/O chip. */
> +static void vt686_enable_serial( void )

Please use the Linux kernel coding style, see
http://linuxbios.org/Development_Guidelines#Coding_Style

You can use the 'indent' tool as a helper (but don't fully trust it)...
> +{
> /* (1) Enter the configuration state. ( Set PCI Function 0 Rx55[1] = 1 ) */
> device_t dev;
> /* First, find the southbridge. Trip the POST card if we don't (does die() do this?)*/

See src/console/console.c, it sets the POST value to 0xff.
> dev = pci_locate_device( PCI_ID( PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686 ), 0 );
> if ( dev == PCI_DEV_INVALID ) {
> outb( 0xf7, 0x80 );

Rather use post_code(0xf7) here...
> die( "Southbridge not found\r\n" ); //Somewhat pointless

Not pointless, die() halts the CPU and you probably don't want to
continue if you don't find the southbridge (?)
> }
> pci_write_config8( dev, 0x85, 0x1f ); //Enable the SuperI/O, SI/O Config, and disable everything else
> /* 2) Configure the chip */
> vt686_sio_write( VT686_POWER, 0x00 ); //Make sure all devs are powered on
> vt686_sio_write( VT686_COM_CFG, 0x00 ); //Set up COMs for normal (non-IR) operation
> vt686_sio_write( VT686_FS, 0x07 ); //Disable Floppy, Enable COM1, Disable COM2 and Parallel Port

This should be somehow configurable. Some people might want to use COM2
(can be configured via some Config.lb)...
> /* Index E2 (aka VT686_FS) ??? Super-I/O Function Select
> 7-5 Reserved (Reads 0)
> 4 Floppy Controller Enable
> 0 Disable (default)
> 1 Enable
> 3 Serial Port 2
> 1 Enable
> 0 Disable (default)
> 2 Serial Port 1
> 0 Disable (default)
> 1 Enable
> 1-0 Parallel Port Mode / Enable
> 00 Unidirectional mode
> 01 ECP
> 10 EPP
> 11 Disable (default) */
> vt686_sio_write( VT686_COM1_BA, 0xfe ); //Set COM1 Base Addr to doc default (3F8)

3F8 -> 0x3F8 (or better 0x3f8, I like lower-case hex numbers, personally).
> vt686_sio_write( VT686_COM_CFG, 0x40 ); //Enable High-Speed mode for COM1
> /* 3) Exit Configuration mode */
> pci_write_config8( dev, 0x85, 0x0d ); //Now set SI/O Config off, enable USB 2/3
>
> +}
> Index: src/southbridge/via/vt686/chip.h
> ===================================================================
> --- src/southbridge/via/vt686/chip.h	(revision 0)
> +++ src/southbridge/via/vt686/chip.h	(revision 0)
> @@ -0,0 +1,37 @@
> +/*
> This file is part of the LinuxBIOS project.
> Copyright (C) 2006 Uwe Hermann
> Copyright (C) 2007 Corey Osgood

Drop my line, this is just some trivial struct declarations...
> This program is free software; you can redistribute it and/or modify
> it under the terms of the GNU General Public License as published by
> the Free Software Foundation; either version 2 of the License, or
> (at your option) any later version.
> This program is distributed in the hope that it will be useful,
> but WITHOUT ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> GNU General Public License for more details.
> You should have received a copy of the GNU General Public License
> along with this program; if not, write to the Free Software
> Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> */
>
> +#ifndef _SUPERIO_VIA_VT686
> +#define _SUPERIO_VIA_VT686
>
> +#include <device/device.h>
> +#include <pc80/keyboard.h>
> +#include <uart8250.h>
>
> +extern struct chip_operations superio_via_vt686_ops;
>
> +struct superio_via_vt686_config {
> struct uart8250 com1, com2;
> struct pc_keyboard keyboard;
>
> +};
>
> +#endif /* _SUPERIO_VIA_VT686 */

HTH, Uwe.

[Corey Osgood]

Uwe Hermann wrote:
> > Index: src/southbridge/via/vt686/Config.lb
> >
> > --- src/southbridge/via/vt686/Config.lb	(revision 0)
> > +++ src/southbridge/via/vt686/Config.lb	(revision 0)
>
> Not sure. I think we usually use the full part names, so this should
> probably be src/southbridge/via/vt82686b/?

In Via's datasheets and the datasheets for the mainboards that I've 
looked at, vt82c686 and vt686 are used interchangeably. We also call it 
vt686 in LBv1, and lm_sensors does too. Linux calls it vt82xxxx, which I 
don't much care for at all, since that also would cover vt8231, etc 
(which linux's driver very well may, but mine doesn't). And vt686 is so 
much easier to write ;)
> How different are vt82686b and vt82686a? Should they become two
> different directories? If not, how should the directory be called?
> vt82686ab, or just vt82686a and we add a comment that it applies to
> the vt82686b as well?

The only difference I've been able to find is that the vt686b supports 
ATA100, whereas the vt686a is only ATA66, which AFAIK should be handled 
by linux, not us. Apart from that, they use the same registers 
(programmed the same way), same ID numbers, etc. If something crops up 
as a major difference, a revision code is on one of the registers, and 
we can use that to determine what we're working with, and what fix to 
apply. Either that, or it can be set up with a #ifdef, and defined in 
auto.c, so we don't have to do runtime southbridge detection. I haven't 
been able to find any official reference at all to a vt82c686 without an 
a or b revision, unless they're referring to either revision, so I'm 
assuming it doesn't exist. Please correct me if I'm wrong!
> Also, shouldn't all of this go into src/superio/via? AFAIK the
> southbridge has a built-in Super I/O, but do we still want to separate
> the Super I/O parts and put them in src/superio/via?
>
> Comments anyone?

With the via vt8231 and vt8235, the Super I/O support is in with the 
southbridge, I was just following this example. It makes sense to me 
personally, since it is still the same part, just two different functions.
> > outb(index, SIO_BASE);
> > /*   b) Read / write data from / to port 3F1 */
>
> 0x3f1
>
> This only writes, drop the comment about reads.

This was actually copied directly from the via datasheets. But yes, I'll 
take care of this
> > +{
> > /* (1) Enter the configuration state. ( Set PCI Function 0 Rx55[1] = 1 ) */
> > device_t dev;
> > /* First, find the southbridge. Trip the POST card if we don't (does die() do this?)*/
>
> See src/console/console.c, it sets the POST value to 0xff.
> > dev = pci_locate_device( PCI_ID( PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686 ), 0 );
> > if ( dev == PCI_DEV_INVALID ) {
> > outb( 0xf7, 0x80 );
>
> Rather use post_code(0xf7) here...

Yeah, the post code was unnecessary, it's been removed entirely. I meant 
to look for die() before sending this, but it slipped my mind. Didn't 
realize we had a post_code(), that could come in handy.
> > die( "Southbridge not found\r\n" ); //Somewhat pointless
>
> Not pointless, die() halts the CPU and you probably don't want to
> continue if you don't find the southbridge (?)

The text is the pointless part, but I meant to remove that comment. 
Sending text output to say that you can't find the southbridge to bring 
up text output...kinda pointless ;)
> > }
> > pci_write_config8( dev, 0x85, 0x1f ); //Enable the SuperI/O, SI/O Config, and disable everything else
> > /* 2) Configure the chip */
> > vt686_sio_write( VT686_POWER, 0x00 ); //Make sure all devs are powered on
> > vt686_sio_write( VT686_COM_CFG, 0x00 ); //Set up COMs for normal (non-IR) operation
> > vt686_sio_write( VT686_FS, 0x07 ); //Disable Floppy, Enable COM1, Disable COM2 and Parallel Port
>
> This should be somehow configurable. Some people might want to use COM2
> (can be configured via some Config.lb)...

The next comment below is from via's datasheets, it's what bits control 
what for that register. The main purpose of this patch is to get serial 
output working on COM1, I can worry about the niceties later. Floppy and 
parallel are also disabled at this point, for the same reason.
> > /* Index E2 (aka VT686_FS) ??? Super-I/O Function Select
> > 7-5 Reserved (Reads 0)
> > 4 Floppy Controller Enable
> > 0 Disable (default)
> > 1 Enable
> > 3 Serial Port 2
> > 1 Enable
> > 0 Disable (default)
> > 2 Serial Port 1
> > 0 Disable (default)
> > 1 Enable
> > 1-0 Parallel Port Mode / Enable
> > 00 Unidirectional mode
> > 01 ECP
> > 10 EPP
> > 11 Disable (default) */

Thanks for all the feedback! A fixed patch is attached. I'll also test 
this on a vt686a once I find my extra BIOS chips for it, but I can't 
imagine any reason it wouldn't work.

-Corey

[Corey Osgood]

Hold off on committing this. I'm having problems with LinuxBIOS hanging 
after entering protected mode (according to the post code). This isn't 
what's causing it, I've dumped in more post codes to check it, but until 
I've got it worked out, please hold off. I could have sworn I tested 
this after a cold reboot, but I guess I only did a reset. Also, I 
submitted the wrong patch the second time, I didn't quite fix 
everything, so there will be another.

Anyone have any idea what causes a hang after protected mode? Is it 
possible that it's because I'm trying to run a dual p3 system with only 
use one cpu? I'm pretty much lost, because it's never even getting into 
auto.c's main(), so it must be in my Config.lb or Options.lb, but I have 
no clue where. I've attached both of these, and I've tried testing with 
only one cpu installed, to no avail.

-Corey

[Corey Osgood]

Forgot to attach the files. here they are.

-Corey

##################################################################
## BEGIN BOILERPLATE - DO NOT EDIT
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus payload) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
# The fallback image uses FALLBACK_SIZE bytes at the end of the ROM

default ROM_SECTION_SIZE   = FALLBACK_SIZE
    default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )

else
# The normal image goes at the beginning of the LinuxBIOS ROM region
# and uses all the remaining space

default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
    default ROM_SECTION_OFFSET = 0
end

##
## Compute where this copy of linuxBIOS will start in the boot rom
##
default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )

##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
default XIP_ROM_SIZE = 65536
default XIP_ROM_BASE = ((( _ROMBASE + ROM_IMAGE_SIZE ) / XIP_ROM_SIZE ) * XIP_ROM_SIZE - XIP_ROM_SIZE )

## END BOILERPLATE
##################################################################

arch i386 end

##
## Build the objects we have code for in this directory.
##

driver mainboard.o
#if HAVE_MP_TABLE 		object mptable.o 	 end
#if HAVE_PIRQ_TABLE 		object irq_tables.o	 end
#if HAVE_ACPI_TABLES 	object acpi_tables.o end
#object reset.o

# Include the VGA option ROM, but only if we're compiled to use it
#if CONFIG_PCI_ROM_RUN
#	if CONFIG_CONSOLE_VGA	
#		object vgarom.S
#	else
#		object no_vgarom.S
#	end
#else
#	object no_vgarom.S
#end

##
## Romcc output
##
makerule ./failover.E
        depends "$(MAINBOARD)/failover.c ./romcc"
        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end

makerule ./failover.inc
        depends "$(MAINBOARD)/failover.c ./romcc"
        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end

makerule ./auto.E
        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
        action  "./romcc -E -mcpu=p3 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
        action  "./romcc    -mcpu=p3 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end

##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds

##
## Build our reset vector (This is where linuxBIOS is entered)
##
if HAVE_FALLBACK_BOOT
    if USE_FALLBACK_IMAGE 
        mainboardinit cpu/x86/16bit/reset16.inc 
        ldscript /cpu/x86/16bit/reset16.lds
    else
        mainboardinit cpu/x86/32bit/reset32.inc 
        ldscript /cpu/x86/32bit/reset32.lds 
    end
else
    mainboardinit cpu/x86/16bit/reset16.inc 
    ldscript /cpu/x86/16bit/reset16.lds
end

### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc

##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds

###
### This is the early phase of linuxBIOS startup 
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
    ldscript /arch/i386/lib/failover.lds 
    mainboardinit ./failover.inc
end

###
### O.k. We aren't just an intermediary anymore!
###

##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc

##
## Include the secondary Configuration files 
##
dir /pc80

if CONFIG_CHIP_NAME
    config chip.h
end

# based on sample config for tyan/s2735
chip northbridge/via/vt694
    device pci_domain 0 on end

chip cpu/intel/socket_PGA370 end
end

uses HAVE_MP_TABLE
uses HAVE_ACPI_TABLES
uses HAVE_PIRQ_TABLE
uses HAVE_FALLBACK_BOOT
uses HAVE_OPTION_TABLE
uses IRQ_SLOT_COUNT
#uses CONFIG_MAX_CPUS
#uses CONFIG_LOGICAL_CPUS
#uses CONFIG_MAX_PHYSICAL_CPUS
#uses CONFIG_IOAPIC
#uses CONFIG_SMP
uses CONFIG_ROM_PAYLOAD
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses STACK_SIZE
uses HEAP_SIZE
uses USE_OPTION_TABLE
#uses LB_CKS_RANGE_START
#uses LB_CKS_RANGE_END
#uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
#uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
#uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses _RAMBASE
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
#uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
#uses CONFIG_CONSOLE_VGA
#uses CONFIG_PCI_ROM_RUN
uses DEBUG
#uses CPU_OPT
#uses CONFIG_IDE

## The default definitions are used for these
uses CONFIG_ROM_PAYLOAD_START
uses PAYLOAD_SIZE

## These are defined in target Config.lb, don't add here
uses USE_FALLBACK_IMAGE
uses ROM_SIZE
uses ROM_IMAGE_SIZE
uses FALLBACK_SIZE
uses LINUXBIOS_EXTRA_VERSION

## These are defined in mainboard Config.lb, don't add here
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE

###
### Build options
###

##
## ROM_SIZE is the size of boot ROM that this board will use.
##
default ROM_SIZE=256*1024
default ROM_IMAGE_SIZE = 65536

##
## Build code for the fallback boot?
##
default HAVE_FALLBACK_BOOT=1
##default FALLBACK_SIZE=131072
default FALLBACK_SIZE=262144

## Delay timer options
##
default CONFIG_UDELAY_TSC=1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1

##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=0
default IRQ_SLOT_COUNT=5

##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default HAVE_MP_TABLE=0

## Build code to export ACPI tables?
default HAVE_ACPI_TABLES=0

##
## Build code to export a CMOS option table?
##
default HAVE_OPTION_TABLE=0

## CMOS checksum definitions (units == bytes)
## These must match the checksum record in cmos.layout
#default LB_CKS_RANGE_START=128
#default LB_CKS_RANGE_END=130
#default LB_CKS_LOC=131

##
## Build code for SMP support
## Only worry about 2 micro processors
## NOTE: CONFIG_MAX_CPUS is the number of LOGICAL CPUs,
##		 so if CONFIG_LOGICAL_CPUS is 1, CONFIG_MAX_CPUS should be 4.
##
#default CONFIG_SMP=0
#default CONFIG_MAX_CPUS=1
#default CONFIG_LOGICAL_CPUS=1
#default CONFIG_MAX_PHYSICAL_CPUS=2

# VGA Console
# NOTE: to initialize VGA, need to copy the VGA option ROM from the factory BIOS
#	    to VGA.rom
#default CONFIG_CONSOLE_VGA=0
#default CONFIG_PCI_ROM_RUN=0

##
## Build code to setup a generic IOAPIC
##
#default CONFIG_IOAPIC=0

##
## Motherboard identification
##
default MAINBOARD_PART_NUMBER="TIGER230"
default MAINBOARD_VENDOR="Tyan"
#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480

###
### LinuxBIOS layout values
###

##
## Use a small 8K stack
##
default STACK_SIZE=0x2000

##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000

##
## CMOS settings not currently supported due to conflicts with factory BIOS
##
default USE_OPTION_TABLE = 0

##
## LinuxBIOS C code runs at this location in RAM
##
default _RAMBASE=0x00004000

##
## Load the payload from the ROM
##
default CONFIG_ROM_PAYLOAD = 1

###
### Defaults of options that you may want to override in the target config file
###

##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
default HOSTCC="gcc -fno-stack-protector"

##
## Disable the gdb stub by default
## 
default CONFIG_GDB_STUB=0

##
## The Serial Console
##

# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1

## Select the serial console baud rate
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800
#default TTYS0_BAUD=2400
#default TTYS0_BAUD=1200

# Select the serial console base port
default TTYS0_BASE=0x3f8

# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3

##
### Select the linuxBIOS loglevel
##
## EMERG      1   system is unusable               
## ALERT      2   action must be taken immediately 
## CRIT       3   critical conditions              
## ERR        4   error conditions                 
## WARNING    5   warning conditions               
## NOTICE     6   normal but significant condition 
## INFO       7   informational                    
## DEBUG      8   debug-level messages             
## SPEW       9   Way too many details

## Request this level of debugging output
default  DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default  MAXIMUM_CONSOLE_LOGLEVEL=8

##
## Select power on after power fail setting
#default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"

## Things we may not have
#default CONFIG_IDE=1

#default DEBUG=1
# default CPU_OPT="-g"
default CONFIG_CHIP_NAME=1

### End Options.lb
end

[Corey Osgood]

Here's the updated version of this patch, which from what I can see 
works perfectly fine, every boot. The description, once again:

This patch is just for initial serial output for the Via vt82c686(a/b) 
southbridge, no more and no less. SMBus and the rest of the SuperI/O 
functions are yet to be written. I've confirmed that this works on Tyan 
S2507 (vt686b), and it should also work fine on vt686a. This is based 
rather loosely on Uwe's code for the SMSC FDC37M60x.

Signed-off-by: Corey Osgood

[Adam Talbot]

Web site update? Should I update the site?

Corey Osgood wrote:
> Here's the updated version of this patch, which from what I can see
> works perfectly fine, every boot. The description, once again:
>
> This patch is just for initial serial output for the Via vt82c686(a/b)
> southbridge, no more and no less. SMBus and the rest of the SuperI/O
> functions are yet to be written. I've confirmed that this works on
> Tyan S2507 (vt686b), and it should also work fine on vt686a. This is
> based rather loosely on Uwe's code for the SMSC FDC37M60x.
> Signed-off-by: Corey Osgood
> Index: src/southbridge/via/vt686/Config.lb
>
> --- src/southbridge/via/vt686/Config.lb	(revision 0)
> +++ src/southbridge/via/vt686/Config.lb	(revision 0)
> @@ -0,0 +1,23 @@
> +##
> +## This file is part of the LinuxBIOS project.
> +##
> +## Copyright (C) 2007 Corey Osgood 
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +##
>
> +config chip.h
> +object superio.o
> Index: src/southbridge/via/vt686/vt686.h
>
> --- src/southbridge/via/vt686/vt686.h	(revision 0)
> +++ src/southbridge/via/vt686/vt686.h	(revision 0)
> @@ -0,0 +1,50 @@
> +/*
> This file is part of the LinuxBIOS project.
> Copyright (C) 2007 Corey Osgood
> This program is free software; you can redistribute it and/or modify
> it under the terms of the GNU General Public License as published by
> the Free Software Foundation; either version 2 of the License, or
> (at your option) any later version.
> This program is distributed in the hope that it will be useful,
> but WITHOUT ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> GNU General Public License for more details.
> You should have received a copy of the GNU General Public License
> along with this program; if not, write to the Free Software
> Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> */
>
> +/* Datasheets:
> Name: VT82C686A "Super South" South Bridge
> Link: http://www.datasheets.org.uk/datasheet.php?article=3510260
> Name: VT82C686B "Super South" South Bridge
> Link: http://www.datasheet4u.com/html/V/T/8/VT82C686B_VIA.pdf.html */
>
> +/* SuperI/0 Configuration Registers */
> +/* Any registers not listed here are for floppy control or are reserved */
> +#define VT686_CFG_PORT	0x3F0
>
> +#define	VT686_FS	0xE2 /* Function Select */
> +#define	VT686_PP_BA	0xE6 /* Parallel Port Base Addr. (def = 378-F) */
> +#define	VT686_COM1_BA	0xE7 /* Serial Port 1 Base Addr. (def =	3F8-F) */
> +#define	VT686_COM2_BA	0xE8 /* Serial Port 2 Base Addr. (def =	2F8-F) */
> +#define	VT686_COM_CFG	0xEE /* Serial Port Configuration */
> +#define	VT686_POWER	0xEF /* Power Down Control */
> +#define	VT686_PPCTRL	0xF0 /* Parallel Port Control */
> +#define	VT686_SPCTRL	0xF1 /* Serial Port Control */
> +#define	VT686_GP_IO	0xFC /* General Purpose I/O */
>
> +/* For reference, used PCI IDs and their names in pci_ids.h */
> +/*
> +PCI_VENDOR_ID_VIA		0x1106
> +PCI_DEVICE_ID_VIA_82C686	0x0686 //Function 0, PCI Config
> +PCI_DEVICE_ID_VIA_82C586_1	0x0571 //Function 1, IDE Controller
> +PCI_DEVICE_ID_VIA_82C586_2	0x3038 //Functions 2 & 3, USB Ports 0-1 & 2-3 Config
> +PCI_DEVICE_ID_VIA_82C586_3	0x3040 //Possible 2nd USB Controller? Not used on my setup/datasheets
> +PCI_DEVICE_ID_VIA_82C686_4	0x3057 //Function 4, Power Management
> +PCI_DEVICE_ID_VIA_82C686_5	0x3058 //Function 5 AC'97 Codec
> +PCI_DEVICE_ID_VIA_82C686_6	0x3068 //Function 6 MC'97 Codec */
> Index: src/southbridge/via/vt686/vt686_early_serial.c
> ===================================================================
> --- src/southbridge/via/vt686/vt686_early_serial.c	(revision 0)
> +++ src/southbridge/via/vt686/vt686_early_serial.c	(revision 0)
> @@ -0,0 +1,83 @@
> +/*
> This file is part of the LinuxBIOS project.
> Copyright (C) 2006 Uwe Hermann
> Copyright (C) 2007 Corey Osgood
> This program is free software; you can redistribute it and/or modify
> it under the terms of the GNU General Public License as published by
> the Free Software Foundation; either version 2 of the License, or
> (at your option) any later version.
> This program is distributed in the hope that it will be useful,
> but WITHOUT ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> GNU General Public License for more details.
> You should have received a copy of the GNU General Public License
> along with this program; if not, write to the Free Software
> Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> */
>
> +/* This has been ported to the Via vt82c686(a/b) from SMSC FDC37M60x by Corey Osgood */
> +/* See vt686.h for more information */
>
> +#include <arch/romcc_io.h>
> +#include <device/pci_ids.h>
> +#include "vt686.h"
>
> +#define SIO_BASE			VT686_CFG_PORT
> +#define SIO_INDEX			SIO_BASE
> +#define SIO_DATA			SIO_BASE+1
>
> +static void vt686_sio_write(uint8_t index, uint8_t value)
> +{
> /* 2) Configure the chip */
> /*   a) Write index to port 0x3F0 */
> outb(index, SIO_BASE);
> /*   b) Read / write data from / to port 0x3F1 */
> outb(value, SIO_DATA);
>
> +}
>
> +/* Enable the peripheral devices on the VT686 Super I/O chip. */
> +static void vt686_enable_serial( void )
> +{
> /* (1) Enter the configuration state. ( Set PCI Function 0 Rx85[1] = 1 ) */
> device_t dev;
> /* First, find the southbridge. Trip the POST card if we don't (does die() do this?)*/
> dev = pci_locate_device( PCI_ID( PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686 ), 0 );
> if ( dev == PCI_DEV_INVALID ) {
> outb( 0xff, 0x80 );
> die( "Southbridge not found\r\n" );
> }
> pci_write_config8( dev, 0x85, 0x1f ); //Enable the SuperI/O, SI/O Config, and disable everything else
> /* 2) Configure the chip */
> vt686_sio_write( VT686_POWER, 0x00 ); //Make sure all devs are powered on. FIXME: only power on used devices
> vt686_sio_write( VT686_COM_CFG, 0x00 ); //Set up COMs for normal (non-IR) operation
> vt686_sio_write( VT686_FS, 0x07 ); //Disable Floppy, Enable COM1, Disable COM2 and Parallel Port
> /* Index E2 (aka VT686_FS) Super-I/O Function Select
> 7-5 Reserved (Reads 0)
> 4 Floppy Controller Enable
> 0 Disable (default)
> 1 Enable
> 3 Serial Port 2
> 1 Enable
> 0 Disable (default)
> 2 Serial Port 1
> 0 Disable (default)
> 1 Enable
> 1-0 Parallel Port Mode / Enable
> 00 Unidirectional mode
> 01 ECP
> 10 EPP
> 11 Disable (default) */
> vt686_sio_write( VT686_COM1_BA, 0xfe ); //Set COM1 Base Addr to doc default (3F8)
> vt686_sio_write( VT686_COM_CFG, 0x40 ); //Enable High-Speed mode for COM1
> /* 3) Exit Configuration mode */
> pci_write_config8( dev, 0x85, 0x0d ); //Now set SI/O Config off, enable USB 2/3
>
> +}
> Index: src/southbridge/via/vt686/chip.h
> ===================================================================
> --- src/southbridge/via/vt686/chip.h	(revision 0)
> +++ src/southbridge/via/vt686/chip.h	(revision 0)
> @@ -0,0 +1,35 @@
> +/*
> This file is part of the LinuxBIOS project.
> Copyright (C) 2007 Corey Osgood
> This program is free software; you can redistribute it and/or modify
> it under the terms of the GNU General Public License as published by
> the Free Software Foundation; either version 2 of the License, or
> (at your option) any later version.
> This program is distributed in the hope that it will be useful,
> but WITHOUT ANY WARRANTY; without even the implied warranty of
> MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> GNU General Public License for more details.
> You should have received a copy of the GNU General Public License
> along with this program; if not, write to the Free Software
> Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> */
>
> +#ifndef _SUPERIO_VIA_VT686
> +#define _SUPERIO_VIA_VT686
>
> +#include <device/device.h>
> +#include <pc80/keyboard.h>
> +#include <uart8250.h>
>
> +extern struct chip_operations superio_via_vt686_ops;
>
> +struct superio_via_vt686_config {
> struct uart8250 com1, com2;
> struct pc_keyboard keyboard;
>
> +};
>
> +#endif /* _SUPERIO_VIA_VT686 */

[Ward Vandewege]

On Mon, Mar 12, 2007 at 05:47:46PM -0700, Adam Talbot wrote:
> Web site update? Should I update the site?

The code should probably be committed to the tree first, don't you think?

Thanks,
Ward.

[Uwe Hermann]

Hi,

On Mon, Mar 12, 2007 at 07:08:32PM -0400, Corey Osgood wrote:
> Here's the updated version of this patch, which from what I can see 
> works perfectly fine, every boot. The description, once again:
>
> This patch is just for initial serial output for the Via vt82c686(a/b) 
> southbridge, no more and no less. SMBus and the rest of the SuperI/O 
> functions are yet to be written. I've confirmed that this works on Tyan 
> S2507 (vt686b), and it should also work fine on vt686a. This is based 
> rather loosely on Uwe's code for the SMSC FDC37M60x.
>
> Signed-off-by: Corey Osgood

OK, I tried this code today on an MSI K7T Turbo (MS-6330), which uses
the VT82C686B southbridge.

I didn't manage to get serial output with this code, yet. I verified
that I can boot Linux with the proprietary BIOS and that I can use
minicom for serial connections to another PC (COM1, 115200 bps, 8N1).

Attached is my quick hack which I used in addition to your patch to be
able to build an image. I abused the tyan/s2735, but it really doesn't
matter which board you use in this case (I think)...

In targets/tyan/s2735/Config.lb I added
  option ROM_SIZE = 256*1024
and set the payload to
  payload /etc/hosts
for a dummy payload (doesn't matter yet).

Maybe I'm missing some important detail in my code? Can you please post
your full patch you use for building an image?
> Index: src/southbridge/via/vt686/vt686_early_serial.c
>
> --- src/southbridge/via/vt686/vt686_early_serial.c	(revision 0)
> +++ src/southbridge/via/vt686/vt686_early_serial.c	(revision 0)

I've been thinking about the name and location of this code. I think
it's better to name the directory vt82c686 (no "a" and no "b") and use it
for both variants (a/b).

Please rename all respective variable names and file names to vt82c686*.

I guess we can keep the code in src/southbridge/via for now (instead of
src/superio/via), I'm still undecided which is better here, but
we can always move the code later...
> +/* Enable the peripheral devices on the VT686 Super I/O chip. */
> +static void vt686_enable_serial( void )
> +{
> /* (1) Enter the configuration state. ( Set PCI Function 0 Rx85[1] = 1 ) */
> device_t dev;
> /* First, find the southbridge. Trip the POST card if we don't (does die() do this?)*/
> dev = pci_locate_device( PCI_ID( PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686 ), 0 );
> if ( dev == PCI_DEV_INVALID ) {
> outb( 0xff, 0x80 );
> die( "Southbridge not found\r\n" );
> }

First I suspected that this code might not work for my board, but the
PCI IDs are ok:

00:07.0 0601: 1106:0686 (rev 40)

I don't have a working POST card at the moment, unfortunately (my old
one is broken), so I cannot verify much here...
> pci_write_config8( dev, 0x85, 0x1f ); //Enable the SuperI/O, SI/O Config, and disable everything else
> /* 2) Configure the chip */
> vt686_sio_write( VT686_POWER, 0x00 ); //Make sure all devs are powered on. FIXME: only power on used devices
> vt686_sio_write( VT686_COM_CFG, 0x00 ); //Set up COMs for normal (non-IR) operation
> vt686_sio_write( VT686_FS, 0x07 ); //Disable Floppy, Enable COM1, Disable COM2 and Parallel Port

This part should check whether COM1 or COM2 was selected by the user,
then only enable that one. No other devices yet (this is
vt686_early_serial.c so we only need serial).

Cheers, Uwe.

[Corey Osgood]

Uwe Hermann wrote:
> OK, I tried this code today on an MSI K7T Turbo (MS-6330), which uses
> the VT82C686B southbridge.
>
> I didn't manage to get serial output with this code, yet. I verified
> that I can boot Linux with the proprietary BIOS and that I can use
> minicom for serial connections to another PC (COM1, 115200 bps, 8N1).

I think this may be your problem, although gcc should have corrected it
or else given an error:
>    w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
>    vt686_enable_serial(SERIAL_DEV, TTYS0_BASE);

this should be vt686_enable_serial();, where it's built into the
southbridge, its location is static afaik.
> Attached is my quick hack which I used in addition to your patch to be
> able to build an image. I abused the tyan/s2735, but it really doesn't
> matter which board you use in this case (I think)...
>
> In targets/tyan/s2735/Config.lb I added
>   option ROM_SIZE = 256*1024
> and set the payload to
>   payload /etc/hosts
> for a dummy payload (doesn't matter yet).
>
> Maybe I'm missing some important detail in my code? Can you please post
> your full patch you use for building an image?

At the moment, my desktop, with all of my linuxbios stuff on it, is in
the middle of a dist-upgrade, with no end in sight (the joys of using
ubuntu 7.04 beta), and I'm headed to bed. I'll post my patch tomorrow
afternoon. I also used tyan s2735 as a base, is it possible that LB is
looking for the P4 cpus and not handling the k7? Or does that happen
after early serial?

Aside from that, it was just tiny changes, like removing all the
mptable/pirq table stuff, and a few other things in Options.lb that were
specific to that board, such as changing over to socket 370 cpus and my
northbridge (which is a work in progress, and isn't important). I also
changed Config.lb in the targets directory to only make a fallback
image, adjusted the fallback image size accordingly, and changed
failover.c in the src/mainboard directory to only boot the fallback image.
> > Index: src/southbridge/via/vt686/vt686_early_serial.c
> >
> > --- src/southbridge/via/vt686/vt686_early_serial.c	(revision 0)
> > +++ src/southbridge/via/vt686/vt686_early_serial.c	(revision 0)
>
> I've been thinking about the name and location of this code. I think
> it's better to name the directory vt82c686 (no "a" and no "b") and use it
> for both variants (a/b).
>
> Please rename all respective variable names and file names to vt82c686*.

Again, I'll handle this later. I assume you'd like VT82C694X (when it's
done) to have the full name also? Or perhaps even vt82c69xx, since it
should also work fine with vt82c693a (although I'd have to review the
docs some more before I'd do this).
> I guess we can keep the code in src/southbridge/via for now (instead of
> src/superio/via), I'm still undecided which is better here, but
> we can always move the code later...

If it does get moved, then via vt8231 and vt8235 should also have their
super i/o functions moved, to avoid confusion and keep consistent.
Frankly, the way I see it, the super i/o is just another function of the
southbridge, and the super i/o code will nearly *always* be used along
with the southbridge, and *never, ever* be used by itself, so why
scatter it around?
> > +/* Enable the peripheral devices on the VT686 Super I/O chip. */
> > +static void vt686_enable_serial( void )
> > +{
> > /* (1) Enter the configuration state. ( Set PCI Function 0 Rx85[1] = 1 ) */
> > device_t dev;
> > /* First, find the southbridge. Trip the POST card if we don't (does die() do this?)*/
> > dev = pci_locate_device( PCI_ID( PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686 ), 0 );
> > if ( dev == PCI_DEV_INVALID ) {
> > outb( 0xff, 0x80 );
> > die( "Southbridge not found\r\n" );
> > }
>
> First I suspected that this code might not work for my board, but the
> PCI IDs are ok:
>
> 00:07.0 0601: 1106:0686 (rev 40)
>
> I don't have a working POST card at the moment, unfortunately (my old
> one is broken), so I cannot verify much here...

At line 95 (or around there), try changing it to this, if it still
doesn't work after the above fix:

if ( dev == PCI_DEV_INVALID ) {
    dev = PCI_DEV(0, 7, 0);
}

I'd say keep the post code too, but without a post card that's
pointless. Finding the southbridge and writing to that register is
essential, if that doesn't happen you're just writing to the read-only
floppy status port, if you don't die(). Perhaps it would be possible to
send a beep or flash a light if the southbridge isn't found, I'll look
into that.
> > pci_write_config8( dev, 0x85, 0x1f ); //Enable the SuperI/O, SI/O Config, and disable everything else
> > /* 2) Configure the chip */
> > vt686_sio_write( VT686_POWER, 0x00 ); //Make sure all devs are powered on. FIXME: only power on used devices
> > vt686_sio_write( VT686_COM_CFG, 0x00 ); //Set up COMs for normal (non-IR) operation
> > vt686_sio_write( VT686_FS, 0x07 ); //Disable Floppy, Enable COM1, Disable COM2 and Parallel Port
>
> This part should check whether COM1 or COM2 was selected by the user,
> then only enable that one. No other devices yet (this is
> vt686_early_serial.c so we only need serial).

For now, I'll just use a #define at the start of the file to set up COM2
instead of COM1, and clean it up later. For the moment, my real focus is
basic setup of the northbridge (which seems to be partially working, but
still failing ram tests), then smbus, and the rest of the chipset
functions, then I can go back and make it all look nice and fully
functional and use Options.lb's defines wherever possible. I plan on
modifying this some before I'm finished, but I figured I'd submit a
patch for it now, since I know there was one email a while back asking
about this chipset.

Cheers,
Corey

[Corey Osgood]

More patches. The full_s2507.patch is everything that I've done 
(including the updated vt82c686). The vt82c686_early_serial.patch is 
just updated to use vt82c686 instead of vt686.

-Corey

[Uwe Hermann]

Hi,

On Wed, Mar 14, 2007 at 01:52:06AM -0400, Corey Osgood wrote:
> > OK, I tried this code today on an MSI K7T Turbo (MS-6330), which uses
> > the VT82C686B southbridge.
> >
> > I didn't manage to get serial output with this code, yet. I verified
> > that I can boot Linux with the proprietary BIOS and that I can use
> > minicom for serial connections to another PC (COM1, 115200 bps, 8N1).

Yay, progress.

With the attached patch I get serial output on my board on serial port 1.
I didn't try COM2, yet.

Not quite sure what the initial problem was, but the current code works
for me. Corey, can you please verify whether it still works on your board?
I made some changes here and there (mostly cosmetic), but maybe I broke
some parts of the code, so please verify on your hardware...

If it works (and if you don't spot further problems in the code) I'd say this
can be committed. Please send an Acked-by if the code looks good to you.
> > I guess we can keep the code in src/southbridge/via for now (instead of
> > src/superio/via), I'm still undecided which is better here, but
> > we can always move the code later...
>
> If it does get moved, then via vt8231 and vt8235 should also have their
> super i/o functions moved, to avoid confusion and keep consistent.

Yes, the current status is not consistent. We should agree upon one
method to do it. In v1 the vt82c686 in separated into southbridge/superio,
but on v2 the vt8231 (for example) is not separated...
> At line 95 (or around there), try changing it to this, if it still
> doesn't work after the above fix:
>
> if ( dev == PCI_DEV_INVALID ) {
>    dev = PCI_DEV(0, 7, 0);
> }

This part worked fine I think, or at least it does in my current patch.

I commented the following lines, they only set values which are already
defaults. I also tested this on real hardware, commenting the lines
doesn't prevent serial output from working...

Uwe.

[Corey Osgood]

Uwe Hermann wrote:
> Yay, progress.
>
> With the attached patch I get serial output on my board on serial port 1.
> I didn't try COM2, yet.
>
> Not quite sure what the initial problem was, but the current code works
> for me. Corey, can you please verify whether it still works on your board?
> I made some changes here and there (mostly cosmetic), but maybe I broke
> some parts of the code, so please verify on your hardware...
>
> If it works (and if you don't spot further problems in the code) I'd say this
> can be committed. Please send an Acked-by if the code looks good to you.

Awesome! I was starting to get concerned that I'd done something that 
only worked on my board. I've got no problem with your changes (although 
I can't _find_ an io base), and the code works fine on my board.

Acked-by: Corey Osgood

One thing though:
> // sbdev = PCI_DEV(0, 7, 0);
> if (sbdev == PCI_DEV_INVALID) {
> /* Serial output is not yet working at this point, but
>  * die() emits the POST code 0xff and halts the CPU, too. */
> die("Southbridge not found.\r\n");
> }

die() in console/console.c does send a post code, but if I try to use 
it, gcc gives an error about function type pointers that I haven't been 
able to track down the cause of. The die() src/arch/i386/lib/console.c 
doesn't send a post code, and that's the one I'm currently using, since 
that's what whichever motherboard I based my code on was using. So, 
either that console.c should get fixed up, or I should figure out why I 
can't use the other one (or even both).

-Corey

[Uwe Hermann]

Committed in r2571, thanks!

On Sat, Mar 17, 2007 at 12:01:28AM -0400, Corey Osgood wrote:
> > If it works (and if you don't spot further problems in the code) I'd say 
> > this
> > can be committed. Please send an Acked-by if the code looks good to you.
>
> Awesome! I was starting to get concerned that I'd done something that 
> only worked on my board. I've got no problem with your changes (although 
> I can't _find_ an io base), and the code works fine on my board.

Yep, iobase is not used yet. I guess we should make these two lines
dependant on the value of iobase?

+       vt82c686_sio_write(VT82C686_SP1, 0xfe);         /* SP1: 0x3f8 */
+       vt82c686_sio_write(VT82C686_SP2, 0xbe);         /* SP2: 0x2f8 */
> die() in console/console.c does send a post code, but if I try to use 
> it, gcc gives an error about function type pointers that I haven't been 
> able to track down the cause of. The die() src/arch/i386/lib/console.c 
> doesn't send a post code, and that's the one I'm currently using, since 
> that's what whichever motherboard I based my code on was using. So, 
> either that console.c should get fixed up, or I should figure out why I 
> can't use the other one (or even both).

Hm, strange. I'll have a look later. Shall we hardcode a post_code()
call in addition of die() for now?

Uwe.

[Corey Osgood]

Uwe Hermann wrote:
> Committed in r2571, thanks!
>
> On Sat, Mar 17, 2007 at 12:01:28AM -0400, Corey Osgood wrote:
> > > If it works (and if you don't spot further problems in the code) I'd say 
> > > this
> > > can be committed. Please send an Acked-by if the code looks good to you.
> >
> > Awesome! I was starting to get concerned that I'd done something that 
> > only worked on my board. I've got no problem with your changes (although 
> > I can't _find_ an io base), and the code works fine on my board.
>
> Yep, iobase is not used yet. I guess we should make these two lines
> dependant on the value of iobase?
>   vt82c686_sio_write(VT82C686_SP1, 0xfe);         /* SP1: 0x3f8 */
>   vt82c686_sio_write(VT82C686_SP2, 0xbe);         /* SP2: 0x2f8 */

Oops, my bad, that wasn't what I meant. But yeah, that will get
done...eventually.
> > die() in console/console.c does send a post code, but if I try to use 
> > it, gcc gives an error about function type pointers that I haven't been 
> > able to track down the cause of. The die() src/arch/i386/lib/console.c 
> > doesn't send a post code, and that's the one I'm currently using, since 
> > that's what whichever motherboard I based my code on was using. So, 
> > either that console.c should get fixed up, or I should figure out why I 
> > can't use the other one (or even both).
>
> Hm, strange. I'll have a look later. Shall we hardcode a post_code()
> call in addition of die() for now?

Can't do that either, for the exact same reason, post_code() isn't in
that particular console.c, it needs to be outb(). Why do we have two
different console.c's, anyways? Is it a romcc or cashe-as-ram thing?

-Corey