Re: [coreboot] ASUS M2N-SLI Deluxe

[Christian Ruppert]

hi guys,

here is 'lspci -tvnn'.
additional cards are marked with PCIE CARD at the begin of line, rest
should be onboard.
i hope it help :)

-[0000:00]-+-00.0  nVidia Corporation MCP55 Memory Controller [10de:0369]
           +-01.0  nVidia Corporation MCP55 LPC Bridge [10de:0360]
           +-01.1  nVidia Corporation MCP55 SMBus [10de:0368]
           +-02.0  nVidia Corporation MCP55 USB Controller [10de:036c]
           +-02.1  nVidia Corporation MCP55 USB Controller [10de:036d]
           +-04.0  nVidia Corporation MCP55 IDE [10de:036e]
           +-05.0  nVidia Corporation MCP55 SATA Controller [10de:037f]
           +-05.1  nVidia Corporation MCP55 SATA Controller [10de:037f]
           +-05.2  nVidia Corporation MCP55 SATA Controller [10de:037f]
           +-06.0-[0000:01]----0b.0  Texas Instruments TSB43AB22/A
IEEE-1394a-2000 Controller (PHY/Link) [104c:8023]
           +-06.1  nVidia Corporation MCP55 High Definition Audio [10de:0371]
           +-08.0  nVidia Corporation MCP55 Ethernet [10de:0373]
           +-09.0  nVidia Corporation MCP55 Ethernet [10de:0373]
PCIE CARD           +-0a.0-[0000:02]----00.0  nVidia Corporation G70
[GeForce 7600 GT] [10de:0391]
           +-0e.0-[0000:03]--
PCIE CARD           +-0f.0-[0000:04]----00.0  nVidia Corporation G70
[GeForce 7600 GT] [10de:0391]
           +-18.0  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
HyperTransport Technology Configuration [1022:1100]
           +-18.1  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
Address Map [1022:1101]
           +-18.2  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
DRAM Controller [1022:1102]
           -18.3  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
Miscellaneous Control [1022:1103]

ASUS M2N-SLI Deluxe

[Paul Menzel]

Dear Christian,

Am Dienstag, den 30.12.2008, 15:27 +0100 schrieb Christian Ruppert:
> here is 'lspci -tvnn'.
> additional cards are marked with PCIE CARD at the begin of line, rest
> should be onboard.
> i hope it help :)
>
> -[0000:00]-+-00.0  nVidia Corporation MCP55 Memory Controller [10de:0369]
>            +-01.0  nVidia Corporation MCP55 LPC Bridge [10de:0360]
>            +-01.1  nVidia Corporation MCP55 SMBus [10de:0368]
>            +-02.0  nVidia Corporation MCP55 USB Controller [10de:036c]
>            +-02.1  nVidia Corporation MCP55 USB Controller [10de:036d]
>            +-04.0  nVidia Corporation MCP55 IDE [10de:036e]
>            +-05.0  nVidia Corporation MCP55 SATA Controller [10de:037f]
>            +-05.1  nVidia Corporation MCP55 SATA Controller [10de:037f]
>            +-05.2  nVidia Corporation MCP55 SATA Controller [10de:037f]
>            +-06.0-[0000:01]----0b.0  Texas Instruments TSB43AB22/A
> IEEE-1394a-2000 Controller (PHY/Link) [104c:8023]
>            +-06.1  nVidia Corporation MCP55 High Definition Audio [10de:0371]
>            +-08.0  nVidia Corporation MCP55 Ethernet [10de:0373]
>            +-09.0  nVidia Corporation MCP55 Ethernet [10de:0373]
> PCIE CARD           +-0a.0-[0000:02]----00.0  nVidia Corporation G70
> [GeForce 7600 GT] [10de:0391]
>            +-0e.0-[0000:03]--
> PCIE CARD           +-0f.0-[0000:04]----00.0  nVidia Corporation G70
> [GeForce 7600 GT] [10de:0391]
>            +-18.0  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> HyperTransport Technology Configuration [1022:1100]
>            +-18.1  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> Address Map [1022:1101]
>            +-18.2  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> DRAM Controller [1022:1102]
>            -18.3  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> Miscellaneous Control [1022:1103]

Thank you. I guess you are referring to [1].

Is it possible that you can test patches to complete the port?

Thanks,

Paul

[1] http://www.coreboot.org/pipermail/coreboot/2007-October/026410.html

ASUS M2N-SLI Deluxe

[Paul Menzel]

Dear Christian,
[I added the list again.]

Am Dienstag, den 30.12.2008, 16:09 +0100 schrieb Christian Ruppert:
> 2008/12/30 Paul Menzel :
> > Am Dienstag, den 30.12.2008, 15:27 +0100 schrieb Christian Ruppert:
> > > here is 'lspci -tvnn'.
> > > additional cards are marked with PCIE CARD at the begin of line, rest
> > > should be onboard.
> > > i hope it help :)
> > >
> > > -[0000:00]-+-00.0  nVidia Corporation MCP55 Memory Controller [10de:0369]
> > >            +-01.0  nVidia Corporation MCP55 LPC Bridge [10de:0360]
> > >            +-01.1  nVidia Corporation MCP55 SMBus [10de:0368]
> > >            +-02.0  nVidia Corporation MCP55 USB Controller [10de:036c]
> > >            +-02.1  nVidia Corporation MCP55 USB Controller [10de:036d]
> > >            +-04.0  nVidia Corporation MCP55 IDE [10de:036e]
> > >            +-05.0  nVidia Corporation MCP55 SATA Controller [10de:037f]
> > >            +-05.1  nVidia Corporation MCP55 SATA Controller [10de:037f]
> > >            +-05.2  nVidia Corporation MCP55 SATA Controller [10de:037f]
> > >            +-06.0-[0000:01]----0b.0  Texas Instruments TSB43AB22/A
> > > IEEE-1394a-2000 Controller (PHY/Link) [104c:8023]
> > >            +-06.1  nVidia Corporation MCP55 High Definition Audio [10de:0371]
> > >            +-08.0  nVidia Corporation MCP55 Ethernet [10de:0373]
> > >            +-09.0  nVidia Corporation MCP55 Ethernet [10de:0373]
> > > PCIE CARD           +-0a.0-[0000:02]----00.0  nVidia Corporation G70
> > > [GeForce 7600 GT] [10de:0391]
> > >            +-0e.0-[0000:03]--
> > > PCIE CARD           +-0f.0-[0000:04]----00.0  nVidia Corporation G70
> > > [GeForce 7600 GT] [10de:0391]
> > >            +-18.0  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> > > HyperTransport Technology Configuration [1022:1100]
> > >            +-18.1  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> > > Address Map [1022:1101]
> > >            +-18.2  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> > > DRAM Controller [1022:1102]
> > >            -18.3  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> > > Miscellaneous Control [1022:1103]
> >
> > Thank you. I guess you are referring to [1].
> >
> > Is it possible that you can test patches to complete the port?
> of course!
> i'd love to help but i have to buy some things before (empty chip,
> nullmodem cable etc.).
> i don't want break my desktop :D

That is a good idea. We will be glad to hear from you, when you got your
stuff and you are all setup. Santa must have been distracted that he did
not get these things for you for Christmas. ;-)
> yep refer to [1].
> > [1] http://www.coreboot.org/pipermail/coreboot/2007-October/026410.html

Thanks,

Paul

PS: Christian, are you knew to the project? If yes and you have time,
could you tell us if you could find everything on the project’s Web site
or could something be improved by for example rearranging or putting
into the FAQ?

ASUS M2N-SLI Deluxe

[Christian Ruppert]

2008/12/30 Paul Menzel :
> Dear Christian,
> [I added the list again.]
>
> Am Dienstag, den 30.12.2008, 16:09 +0100 schrieb Christian Ruppert:
> > 2008/12/30 Paul Menzel :
> > > Am Dienstag, den 30.12.2008, 15:27 +0100 schrieb Christian Ruppert:
> > > > here is 'lspci -tvnn'.
> > > > additional cards are marked with PCIE CARD at the begin of line, rest
> > > > should be onboard.
> > > > i hope it help :)
> > > >
> > > > -[0000:00]-+-00.0  nVidia Corporation MCP55 Memory Controller [10de:0369]
> > > >            +-01.0  nVidia Corporation MCP55 LPC Bridge [10de:0360]
> > > >            +-01.1  nVidia Corporation MCP55 SMBus [10de:0368]
> > > >            +-02.0  nVidia Corporation MCP55 USB Controller [10de:036c]
> > > >            +-02.1  nVidia Corporation MCP55 USB Controller [10de:036d]
> > > >            +-04.0  nVidia Corporation MCP55 IDE [10de:036e]
> > > >            +-05.0  nVidia Corporation MCP55 SATA Controller [10de:037f]
> > > >            +-05.1  nVidia Corporation MCP55 SATA Controller [10de:037f]
> > > >            +-05.2  nVidia Corporation MCP55 SATA Controller [10de:037f]
> > > >            +-06.0-[0000:01]----0b.0  Texas Instruments TSB43AB22/A
> > > > IEEE-1394a-2000 Controller (PHY/Link) [104c:8023]
> > > >            +-06.1  nVidia Corporation MCP55 High Definition Audio [10de:0371]
> > > >            +-08.0  nVidia Corporation MCP55 Ethernet [10de:0373]
> > > >            +-09.0  nVidia Corporation MCP55 Ethernet [10de:0373]
> > > > PCIE CARD           +-0a.0-[0000:02]----00.0  nVidia Corporation G70
> > > > [GeForce 7600 GT] [10de:0391]
> > > >            +-0e.0-[0000:03]--
> > > > PCIE CARD           +-0f.0-[0000:04]----00.0  nVidia Corporation G70
> > > > [GeForce 7600 GT] [10de:0391]
> > > >            +-18.0  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> > > > HyperTransport Technology Configuration [1022:1100]
> > > >            +-18.1  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> > > > Address Map [1022:1101]
> > > >            +-18.2  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> > > > DRAM Controller [1022:1102]
> > > >            -18.3  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> > > > Miscellaneous Control [1022:1103]
> > >
> > > Thank you. I guess you are referring to [1].
> > >
> > > Is it possible that you can test patches to complete the port?
> > of course!
> > i'd love to help but i have to buy some things before (empty chip,
> > nullmodem cable etc.).
> > i don't want break my desktop :D
>
> That is a good idea. We will be glad to hear from you, when you got your
> stuff and you are all setup. Santa must have been distracted that he did
> not get these things for you for Christmas. ;-)
> > yep refer to [1].
> > > [1] http://www.coreboot.org/pipermail/coreboot/2007-October/026410.html
>
> Thanks,
>
> Paul
>
> PS: Christian, are you knew to the project? If yes and you have time,
> could you tell us if you could find everything on the project's Web site
> or could something be improved by for example rearranging or putting
> into the FAQ?

ok.. i've my backup ICs, PLCC extractor and a nullmodem cable :)
first test failed :/
i've used the lastest svn rev. with the m2n-sli-deluxe patch, as payload i've
defined /dev/zero (because i just want test the bios before i test
everything else).

after poweron followed directly and automatic a poweroff so i think it
isn't right.
i tried it again and no poweroff but a black screen (i use a PCIE graphics card
here with DVI dunno if that makes any differences).

it would be fine if we could get together in #coreboot :)

ASUS M2N-SLI Deluxe

[Christian Ruppert]

ok guys,

a little summary from my side:

i've tried the patch from uwe [1] but there are some issues with the
baud rate and also the same problem as fred [2] had but with a
different output.

the baud problem could be solved with a small workaround: just change
to 57600 in minicom but leave 115200 in the bios source.
uwe wrote then a second patch (see attachment, works with the lastest
svn rev. (remove the old patch before apply the new one)) which fixed
the baud problem and other stuff but not the "poweroff" problem.

my first boot log was:

coreboot-2.0.0.0Fallback Fr 2. Jan 17:10:59 CET 2009 starting...
*sysinfo range: [000cf000,000cf730)
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling UP settings
coherent_ht_finalize
done
core0 started:
started ap apicid:  01
SBLink=00
NC node|link=00
begin msr fid, vid 3107121207110202
Current fid_cur: 0x2, fid_max: 0x11
Requested fid_new: 0x11
FidVid table step fidvid: 0xe
200MHZ step fidvid: 0x10
100MHZ step fidvid: 0x11
end   msr fid, vid 3107120707110211
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x807f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x1
after optimize_link_read_pointers_chain, reset_needed=0x1
mcp55_num:01

uwe told me to remove all useless hardware during these tests but no difference.

i hope that somebody find a solution to get a working bios for this board.

thats all for now.. i'll keep you up2date if something happens.

[1] http://www.coreboot.org/pipermail/coreboot/2007-October/026410.html
[2] http://thread.gmane.org/gmane.linux.bios/45265/focus=45311

ASUS M2N-SLI Deluxe

[Myles Watson]

> -----Original Message-----
> From: coreboot-bounces+mylesgw=[e-mail] [mailto:coreboot-
> bounces+mylesgw=[e-mail]] On Behalf Of Christian Ruppert
> Sent: Friday, January 02, 2009 11:51 AM
> To: [e-mail]
> Subject: Re: [coreboot] ASUS M2N-SLI Deluxe
>
> ok guys,
>
> a little summary from my side:
>
> i've tried the patch from uwe [1] but there are some issues with the
> baud rate and also the same problem as fred [2] had but with a
> different output.
>
> the baud problem could be solved with a small workaround: just change
> to 57600 in minicom but leave 115200 in the bios source.
> uwe wrote then a second patch (see attachment, works with the lastest
> svn rev. (remove the old patch before apply the new one)) which fixed
> the baud problem and other stuff but not the "poweroff" problem.
>
> my first boot log was:
>
> coreboot-2.0.0.0Fallback Fr 2. Jan 17:10:59 CET 2009 starting...
> *sysinfo range: [000cf000,000cf730)
> bsp_apicid=00
> Enabling routing table for node 00 done.
> Enabling UP settings
> coherent_ht_finalize
> done
> core0 started:
> started ap apicid:  01
> SBLink=00
> NC node|link=00
> begin msr fid, vid 3107121207110202
> Current fid_cur: 0x2, fid_max: 0x11
> Requested fid_new: 0x11
> FidVid table step fidvid: 0xe
> 200MHZ step fidvid: 0x10
> 100MHZ step fidvid: 0x11
> end   msr fid, vid 3107120707110211
> entering optimize_link_incoherent_ht
> sysinfo->link_pair_num=0x1
> entering ht_optimize_link
> pos=0x8a, unfiltered freq_cap=0x8075
> pos=0x8a, filtered freq_cap=0x75
> pos=0x52, unfiltered freq_cap=0x807f
> pos=0x52, filtered freq_cap=0x7f
> freq_cap1=0x75, freq_cap2=0x7f
> dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
> dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
> width_cap1=0x11, width_cap2=0x11
> dev1 input ln_width1=0x4, ln_width2=0x4
> dev1 input width=0x1
> dev1 output ln_width1=0x4, ln_width2=0x4
> dev1 input|output width=0x11
> old dev1 input|output width=0x11
> dev2 input|output width=0x11
> old dev2 input|output width=0x11
> after ht_optimize_link for link pair 0, reset_needed=0x1
> after optimize_link_read_pointers_chain, reset_needed=0x1
> mcp55_num:01

It looks like you're getting to the first reset, then that isn't working.
Have you tried commenting out the reset at that point to see how much
farther you get?

The reset is to make the HT optimizations take effect, so it will be slower
but should continue.

Thanks,
Myles

ASUS M2N-SLI Deluxe

[Christian Ruppert]

2009/1/2 Myles Watson :
> > -----Original Message-----
> > From: coreboot-bounces+mylesgw=[e-mail] [mailto:coreboot-
> > bounces+mylesgw=[e-mail]] On Behalf Of Christian Ruppert
> > Sent: Friday, January 02, 2009 11:51 AM
> > To: [e-mail]
> > Subject: Re: [coreboot] ASUS M2N-SLI Deluxe
> >
> > ok guys,
> >
> > a little summary from my side:
> >
> > i've tried the patch from uwe [1] but there are some issues with the
> > baud rate and also the same problem as fred [2] had but with a
> > different output.
> >
> > the baud problem could be solved with a small workaround: just change
> > to 57600 in minicom but leave 115200 in the bios source.
> > uwe wrote then a second patch (see attachment, works with the lastest
> > svn rev. (remove the old patch before apply the new one)) which fixed
> > the baud problem and other stuff but not the "poweroff" problem.
> >
> > my first boot log was:
> >
> > coreboot-2.0.0.0Fallback Fr 2. Jan 17:10:59 CET 2009 starting...
> > *sysinfo range: [000cf000,000cf730)
> > bsp_apicid=00
> > Enabling routing table for node 00 done.
> > Enabling UP settings
> > coherent_ht_finalize
> > done
> > core0 started:
> > started ap apicid:  01
> > SBLink=00
> > NC node|link=00
> > begin msr fid, vid 3107121207110202
> > Current fid_cur: 0x2, fid_max: 0x11
> > Requested fid_new: 0x11
> > FidVid table step fidvid: 0xe
> > 200MHZ step fidvid: 0x10
> > 100MHZ step fidvid: 0x11
> > end   msr fid, vid 3107120707110211
> > entering optimize_link_incoherent_ht
> > sysinfo->link_pair_num=0x1
> > entering ht_optimize_link
> > pos=0x8a, unfiltered freq_cap=0x8075
> > pos=0x8a, filtered freq_cap=0x75
> > pos=0x52, unfiltered freq_cap=0x807f
> > pos=0x52, filtered freq_cap=0x7f
> > freq_cap1=0x75, freq_cap2=0x7f
> > dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
> > dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
> > width_cap1=0x11, width_cap2=0x11
> > dev1 input ln_width1=0x4, ln_width2=0x4
> > dev1 input width=0x1
> > dev1 output ln_width1=0x4, ln_width2=0x4
> > dev1 input|output width=0x11
> > old dev1 input|output width=0x11
> > dev2 input|output width=0x11
> > old dev2 input|output width=0x11
> > after ht_optimize_link for link pair 0, reset_needed=0x1
> > after optimize_link_read_pointers_chain, reset_needed=0x1
> > mcp55_num:01
>
> It looks like you're getting to the first reset, then that isn't working.
> Have you tried commenting out the reset at that point to see how much
> farther you get?
>
> The reset is to make the HT optimizations take effect, so it will be slower
> but should continue.
>
> Thanks,
> Myles

i commented soft_reset(); in cache_as_ram_auto.c but still the same.

ASUS M2N-SLI Deluxe

[Christian Ruppert]

now i know where it stops.
i wrote a few debug prints in sothbridge/nvidia/mcp55/mcp55_early_setup_car.c
but don't slap me because i haven't checked all of these variable types %)
anyway.. i hope it help.

the numbers at the beginning of the line are line numbers.

the same log as i posted...
mcp55_num:01

in file src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c:
327: for(j=0; j<mcp55_num; j++)
327: j=0
328: mcp55_early_pcie_setup(0, 0, 10240, 0);
330: setup_resource_map_x_offset(4294923544, 160, 00000000, 0);

332: for(i=0; i<3; i++) { // three SATA
332: i=0
333: setup_resource_map_x_offset(4294923400, 36, 00000000, 0, 0)
332: i=1
333: setup_resource_map_x_offset(4294923400, 36, 00001000, 0, 1)
332: i=2
333: setup_resource_map_x_offset(4294923400, 36, 00002000, 0, 2)

336: busn[j] = 0
337: setup_resource_map_x_offset(ffff5278, 132, 00000000, 0)

347: setup_resource_map_x_offset(ffff5208, 28, 00000000, 0)

_END_

so coreboot doesn't leave 'static void mcp55_early_setup(unsigned
mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned
*pci_e_x)' in mcp55_early_setup_car.c

ASUS M2N-SLI Deluxe

[Christian Ruppert]

i tested it again with RES_DEBUG and CONFIG_USE_PRINTK_IN_CAR.

coreboot-2.0.0.0Fallback Sun Jan  4 15:15:44 CET 2009 starting...
*sysinfo range: [000cf000,000cf730)
bsp_apicid=00
Enabling routing table for node 00 done.
Enabling UP settings
coherent_ht_finalize
done
core0 started:
started ap apicid:  01
SBLink=00
NC node|link=00
begin msr fid, vid 3107121207110202
Current fid_cur: 0x2, fid_max: 0x11
Requested fid_new: 0x11
FidVid table step fidvid: 0xe
200MHZ step fidvid: 0x10
100MHZ step fidvid: 0x11
end   msr fid, vid 3107120707110211
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x52, unfiltered freq_cap=0x807f
pos=0x52, filtered freq_cap=0x7f
freq_cap1=0x75, freq_cap2=0x7f
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x1
after optimize_link_read_pointers_chain, reset_needed=0x1
mcp55_num:01

181: from mcp55_early_setup_car.c:static void mcp55_early_setup()
327: for(j=0; j<mcp55_num; j++)
327: j=0
328: mcp55_early_pcie_setup();
330: setup_resource_map_x_offset();

setting up resource map ex offset....
0000: 20 00002010 <- & 0007ffff | 0ff78000
0001: 20 000020a4 <- & ffedffff | 00012000
0002: 20 000020ac <- & fffffdff | 00000200
0003: 20 000020b4 <- & fffffffd | 00000002
0004: 20 00002824 <- & c0f0f08f | 26020230
0005: 20 00002834 <- & 00000000 | 22222222
0006: 20 00002808 <- & 7fffffff | 00000000
0007: 20 0000282c <- & 7fffffff | 80000000
0008: 20 000028cc <- & fffff9ff | 00000000
0009: 20 00002830 <- & 8fffffff | 40000000
000a: 20 000028cc <- & fffff9ff | 00000200
000b: 20 00002830 <- & 8fffffff | 40000000
000c: 20 000028cc <- & fffff9ff | 00000400
000d: 20 00002830 <- & 8fffffff | 40000000
000e: 20 00002874 <- & ffff0ff5 | 0000f000
000f: 20 00002878 <- & ff00ff00 | 00100010
0010: 20 0000287c <- & ff0ff0ff | 00500500
0011: 20 00002880 <- & ffffffe7 | 00000000
0012: 20 00002860 <- & ffcfffff | 00300000
0013: 20 00002890 <- & ffff00ff | 0000ff00
0014: 20 0000289c <- & ff00ffff | 00070000
0015: 10 00000040 <- & 00000000 | cb8410de
0016: 10 00000048 <- & ffffdced | 00002002
0017: 10 00000078 <- & ffffff8e | 00000011
0018: 10 00000080 <- & ffff0000 | 00009923
0019: 10 00000088 <- & fffffffe | 00000000
001a: 10 0000008c <- & ffff0000 | 0000007f
001b: 10 000000dc <- & fffeffff | 00010000
001c: 10 00008040 <- & 00000000 | cb8410de
001d: 10 00008074 <- & ffffff7b | 00000084
001e: 10 000080f8 <- & ffffffcf | 00000010
001f: 10 000090c4 <- & fffffffe | 00000001
0020: 10 000090f0 <- & 7ffffffd | 00000002
0021: 10 000090f8 <- & ffffffcf | 00000010
0022: 10 00040040 <- & 00000000 | cb8410de
0023: 10 00040068 <- & ffffff00 | 000000ff
0024: 10 000400f8 <- & ffffffbf | 00000040
0025: 10 00048040 <- & 00000000 | cb8410de
0026: 10 00048068 <- & ffffff00 | 000000ff
0027: 10 000480f8 <- & ffffffbf | 00000040
done.

332: for(i=0; i<3; i++) { // three SATA
332: i=0
333: setup_resource_map_x_offset()

setting up resource map ex offset....
0000: 10 00028040 <- & 00000000 | cb8410de
0001: 10 00028050 <- & fffffffc | 00000003
0002: 10 00028064 <- & fffffffe | 00000001
0003: 10 00028070 <- & fff0ffff | 00040000
0004: 10 000280ac <- & fffff0ff | 00000100
0005: 10 0002807c <- & ffffffef | 00000000
0006: 10 000280c8 <- & ff00ff00 | 000a000a
0007: 10 000280d0 <- & f0ffffff | 03000000
0008: 10 000280e0 <- & f0ffffff | 03000000
done.

332: i=1
333: setup_resource_map_x_offset()

setting up resource map ex offset....
0000: 10 00029040 <- & 00000000 | cb8410de
0001: 10 00029050 <- & fffffffc | 00000003
0002: 10 00029064 <- & fffffffe | 00000001
0003: 10 00029070 <- & fff0ffff | 00040000
0004: 10 000290ac <- & fffff0ff | 00000100
0005: 10 0002907c <- & ffffffef | 00000000
0006: 10 000290c8 <- & ff00ff00 | 000a000a
0007: 10 000290d0 <- & f0ffffff | 03000000
0008: 10 000290e0 <- & f0ffffff | 03000000
done.

332: i=2
333: setup_resource_map_x_offset()

setting up resource map ex offset....
0000: 10 0002a040 <- & 00000000 | cb8410de
0001: 10 0002a050 <- & fffffffc | 00000003
0002: 10 0002a064 <- & fffffffe | 00000001
0003: 10 0002a070 <- & fff0ffff | 00040000
0004: 10 0002a0ac <- & fffff0ff | 00000100
0005: 10 0002a07c <- & ffffffef | 00000000
0006: 10 0002a0c8 <- & ff00ff00 | 000a000a
0007: 10 0002a0d0 <- & f0ffffff | 03000000
0008: 10 0002a0e0 <- & f0ffffff | 03000000
done.

336: busn[j] = 0
337: setup_resource_map_x_offset()

setting up resource map ex offset....
0000: 10 00009040 <- & 00000000 | cb8410de
0001: 10 000090e0 <- & fffffeff | 00000000
0002: 10 000090e4 <- & fffffffb | 00000000
0003: 10 000090e8 <- & ffa9c8ff | 00003000
0004: 10 00020040 <- & 00000000 | cb8410de
0005: 10 000200f8 <- & ffffffcf | 00000010
0006: 10 00010040 <- & 00000000 | cb8410de
0007: 10 00011040 <- & 00000000 | cb8410de
0008: 10 00011064 <- & f87fffff | 05000000
0009: 10 00011078 <- & ffc07fff | 00360000
000a: 10 00011068 <- & fe00d03f | 013f2c00
000b: 10 00011070 <- & fff7ffff | 00080000
000c: 10 0001107c <- & fffff00f | 00000570
000d: 10 000110f8 <- & ffffffcf | 00000010
000e: 10 00030004 <- & fffffefb | 00000104
000f: 10 0003003c <- & f5ffffff | 0a000000
0010: 10 00030040 <- & 00c8ffff | 07330000
0011: 10 00030048 <- & fffffff8 | 00000005
0012: 10 0003004c <- & fe02ffff | 004c0000
0013: 10 00030074 <- & ffffffc0 | 00000000
0014: 10 000300c0 <- & 00000000 | cb8410de
0015: 10 000300c4 <- & fffffff8 | 00000007
0016: 10 00008078 <- & c0ffffff | 19000000
0017: 10 00031040 <- & 00000000 | cb8410de
0018: 22 000024e5 <- & 00000000 | 00000044
0019: 22 000024e6 <- & 00000000 | 00000044
001a: 22 000024e7 <- & 00000000 | 00000044
001b: 22 000024e8 <- & 00000000 | 00000044
001c: 22 000024fb <- & 00000000 | 00000060
001d: 22 000024fc <- & 00000000 | 00000060
001e: 22 000024d5 <- & fffffff3 | 00000008
001f: 22 000024d6 <- & fffffff3 | 00000008
0020: 22 000024ee <- & fffffff3 | 00000008
done.

346: setup_resource_map_x_offset()

setting up resource map ex offset....
0000: 10 00000074 <- & fffff00f | 000009d0
0001: 10 00008074 <- & ffff7fff | 00008000
0002: 20 00002448 <- & fffeffff | 00010000
0003: 20 00002860 <- & ffffff00 | 00000012
0004: 10 000090e4 <- & ffafffff | 00500000
0005: 22 000024c4 <- & ffffff00 | 00000004
0006: 22 000024c4 <- & ffffff00 | 00000005