Hi Alex,
On 07.06.19 08:56, Alex Feinman wrote:
I've checked the upper 16 MB - simply dumped the block at 0xff9f0000 (0xff000000 is the last 16 MB + MRC cache region offset 0x9f0000 from the layout file ) where in my image the MRC cache region resides (I can confirm it's there by dumping the image from flash). The data I read from the supposed memory mapping is all 0xff.
IIRC, you already confirmed with an external programmer that the data is written at this location, right? If the data is there but not memory mapped, maybe that offset isn't covered by the BIOS region in IFD?
fmd and .config files are attached
I didn't spot anything problematic there. But as you don't have CONFIG_VBOOT selected, you could also try a much simpler FMD file or just the automatically generated default, by unsetting CONFIG_FMDFILE.
Nico
Hi Nico,
That's an interesting idea (IFD). Here is a dump of my IFD, but the problem is - I am not sure what the regions are and what they should be. Perhaps I need a region that includes my MRC cache (0x9f0000)?
File build/coreboot.rom is 16777216 bytes Found Flash Descriptor signature at 0x00000010 FLMAP0: 0x00040003 NR: 0 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x42100208 ISL: 0x42 FPSBA: 0x100 NM: 2 FMBA: 0x80 FLMAP2: 0x00310330 PSL: 0x3103 FMSBA: 0x300 FLUMAP1: 0x000006df
Found Region Section FLREG0: 0x00000000 FLREG1: 0x0fff0a00 FLREG2: 0x09ff0003 FLREG3: 0x00020001 FLREG4: 0x00007fff
Found Component Section FLCOMP 0x365c00f5 Read ID/Read Status Clock Frequency: unknown<6>MHz Write/Erase Clock Frequency: unknown<6>MHz Fast Read Clock Frequency: unknown<2>MHz FLILL 0xad604221 FLPB 0xc7c4b9b7
Found PCH Strap Section PCHSTRP0: 0x00220002 PCHSTRP1: 0x44000100 PCHSTRP2: 0x00010000 PCHSTRP3: 0x00000000 PCHSTRP4: 0x00000000 PCHSTRP5: 0x00010000 PCHSTRP6: 0x00000100 PCHSTRP7: 0x00000000 PCHSTRP8: 0x00000000 PCHSTRP9: 0x00000000 PCHSTRP10: 0x00030000 PCHSTRP11: 0x00000100 PCHSTRP12: 0x00000000 PCHSTRP13: 0x00000000 PCHSTRP14: 0x00000000 PCHSTRP15: 0x00010000
Found Master Section FLMSTR1: 0xffffff00 FLMSTR2: 0xffffff00 FLMSTR3: 0xffffff00
Found Processor Strap Section ????: 0x00001000 ????: 0x00108002 ????: 0x00000210 ????: 0xffffffff
________________________________________ From: Nico Huber nico.h@gmx.de Sent: Friday, June 7, 2019 2:41 AM To: Alex Feinman; coreboot@coreboot.org Subject: Re: [coreboot] MRC cache save/readback failure (SKL/KBL)
Hi Alex,
On 07.06.19 08:56, Alex Feinman wrote:
I've checked the upper 16 MB - simply dumped the block at 0xff9f0000 (0xff000000 is the last 16 MB + MRC cache region offset 0x9f0000 from the layout file ) where in my image the MRC cache region resides (I can confirm it's there by dumping the image from flash). The data I read from the supposed memory mapping is all 0xff.
IIRC, you already confirmed with an external programmer that the data is written at this location, right? If the data is there but not memory mapped, maybe that offset isn't covered by the BIOS region in IFD?
fmd and .config files are attached
I didn't spot anything problematic there. But as you don't have CONFIG_VBOOT selected, you could also try a much simpler FMD file or just the automatically generated default, by unsetting CONFIG_FMDFILE.
Nico
Indeed this was it. I had a mismatch between the IFD and FMD. As a result my MRC cache was in the IFD ME region. Obviously the mapper masks ME region. I think I also have a problem with ME being too large for 16 MB chip (it's 10 MB alone). I might have to expand the storage on my board. Thank you for looking into this
Alex
________________________________________ From: Alex Feinman alexfeinman@hotmail.com Sent: Friday, June 7, 2019 2:58 AM To: Nico Huber; coreboot@coreboot.org Subject: [coreboot] Re: MRC cache save/readback failure (SKL/KBL)
Hi Nico,
That's an interesting idea (IFD). Here is a dump of my IFD, but the problem is - I am not sure what the regions are and what they should be. Perhaps I need a region that includes my MRC cache (0x9f0000)?
File build/coreboot.rom is 16777216 bytes Found Flash Descriptor signature at 0x00000010 FLMAP0: 0x00040003 NR: 0 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x42100208 ISL: 0x42 FPSBA: 0x100 NM: 2 FMBA: 0x80 FLMAP2: 0x00310330 PSL: 0x3103 FMSBA: 0x300 FLUMAP1: 0x000006df
Found Region Section FLREG0: 0x00000000 FLREG1: 0x0fff0a00 FLREG2: 0x09ff0003 FLREG3: 0x00020001 FLREG4: 0x00007fff
Found Component Section FLCOMP 0x365c00f5 Read ID/Read Status Clock Frequency: unknown<6>MHz Write/Erase Clock Frequency: unknown<6>MHz Fast Read Clock Frequency: unknown<2>MHz FLILL 0xad604221 FLPB 0xc7c4b9b7
Found PCH Strap Section PCHSTRP0: 0x00220002 PCHSTRP1: 0x44000100 PCHSTRP2: 0x00010000 PCHSTRP3: 0x00000000 PCHSTRP4: 0x00000000 PCHSTRP5: 0x00010000 PCHSTRP6: 0x00000100 PCHSTRP7: 0x00000000 PCHSTRP8: 0x00000000 PCHSTRP9: 0x00000000 PCHSTRP10: 0x00030000 PCHSTRP11: 0x00000100 PCHSTRP12: 0x00000000 PCHSTRP13: 0x00000000 PCHSTRP14: 0x00000000 PCHSTRP15: 0x00010000
Found Master Section FLMSTR1: 0xffffff00 FLMSTR2: 0xffffff00 FLMSTR3: 0xffffff00
Found Processor Strap Section ????: 0x00001000 ????: 0x00108002 ????: 0x00000210 ????: 0xffffffff
________________________________________ From: Nico Huber nico.h@gmx.de Sent: Friday, June 7, 2019 2:41 AM To: Alex Feinman; coreboot@coreboot.org Subject: Re: [coreboot] MRC cache save/readback failure (SKL/KBL)
Hi Alex,
On 07.06.19 08:56, Alex Feinman wrote:
I've checked the upper 16 MB - simply dumped the block at 0xff9f0000 (0xff000000 is the last 16 MB + MRC cache region offset 0x9f0000 from the layout file ) where in my image the MRC cache region resides (I can confirm it's there by dumping the image from flash). The data I read from the supposed memory mapping is all 0xff.
IIRC, you already confirmed with an external programmer that the data is written at this location, right? If the data is there but not memory mapped, maybe that offset isn't covered by the BIOS region in IFD?
fmd and .config files are attached
I didn't spot anything problematic there. But as you don't have CONFIG_VBOOT selected, you could also try a much simpler FMD file or just the automatically generated default, by unsetting CONFIG_FMDFILE.
Nico _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
On 07.06.19 16:24, Alex Feinman wrote:
Indeed this was it. I had a mismatch between the IFD and FMD. As a result my MRC cache was in the IFD ME region. Obviously the mapper masks ME region. I think I also have a problem with ME being too large for 16 MB chip (it's 10 MB alone). I might have to expand the storage on my board. Thank you for looking into this
ah, nice that you could fix it. The ME firmware usually gets 1.5 or 5MiB depending on the version (w/ or w/o AMT for instance). You can probably just decrease its size, but make sure that you don't cut into anything that isn't ff (or maybe 00, not sure).
Nico
-
Alex Feinman -
Nico Huber