Issue #583 has been reported by Keith Hui.
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
Issue #583 has been updated by Bill XIE.
File autoport-p8z77v-gb83fac3e1c74-dirty.tgz added
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2051
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB)
Issue #583 has been updated by Bill XIE.
File cbmem-0-2-7-noPCIEX1_2.log added
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2052
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) cbmem-0-2-7-noPCIEX1_2.log (81.2 KB)
Issue #583 has been updated by Keith Hui.
File p8z77-v-pcielane-gpio-probe-map.png added
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2057
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) p8z77-v-pcielane-gpio-probe-map.png (257 KB)
Issue #583 has been updated by Bill XIE.
File p8z77v-r1.02.png added
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2058
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) p8z77-v-pcielane-gpio-probe-map.png (257 KB) p8z77v-r1.02.png (3.09 MB)
Issue #583 has been updated by Keith Hui.
File p8z77v-r1.02-where-to-probe.png added
Attached gimped photo shows where to probe instead. The numbers are for X_QSW_SEL[#].
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2059
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) p8z77-v-pcielane-gpio-probe-map.png (257 KB) p8z77v-r1.02.png (3.09 MB) p8z77v-r1.02-where-to-probe.png (3.09 MB)
Issue #583 has been updated by Keith Hui.
% Done changed from 0 to 90 Estimated time set to 15.00 h Affected versions main added
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2060
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Affected versions: main * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) p8z77-v-pcielane-gpio-probe-map.png (257 KB) p8z77v-r1.02.png (3.09 MB) p8z77v-r1.02-where-to-probe.png (3.09 MB)
Issue #583 has been updated by Keith Hui.
IFD reflash process has been determined and implemented. Test underway. A mode where PCIEX16_3 operates in x2, not available with vendor BIOS, is added. Hardware has been tested to be capable of this mode, but PCIEX1_1 will be disabled.
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2061
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Affected versions: main * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) p8z77-v-pcielane-gpio-probe-map.png (257 KB) p8z77v-r1.02.png (3.09 MB) p8z77v-r1.02-where-to-probe.png (3.09 MB)
Issue #583 has been updated by Bill XIE.
File p8z77v-ifd.bin added File p8z77v-ifdprog.log added
Keith Hui wrote in #note-7:
IFD reflash process has been determined and implemented. Test underway. A mode where PCIEX16_3 operates in x2, not available with vendor BIOS, is added. Hardware has been tested to be capable of this mode, but PCIEX1_1 will be disabled.
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2069
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Affected versions: main * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) p8z77-v-pcielane-gpio-probe-map.png (257 KB) p8z77v-r1.02.png (3.09 MB) p8z77v-r1.02-where-to-probe.png (3.09 MB) p8z77v-ifd.bin (4 KB) p8z77v-ifdprog.log (103 KB)
Issue #583 has been updated by Bill XIE.
File p8z77v-ifdprog-rdev.log added
Bill XIE wrote in #note-8:
Keith Hui wrote in #note-7:
IFD reflash process has been determined and implemented. Test underway. A mode where PCIEX16_3 operates in x2, not available with vendor BIOS, is added. Hardware has been tested to be capable of this mode, but PCIEX1_1 will be disabled.
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2070
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Affected versions: main * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) p8z77-v-pcielane-gpio-probe-map.png (257 KB) p8z77v-r1.02.png (3.09 MB) p8z77v-r1.02-where-to-probe.png (3.09 MB) p8z77v-ifd.bin (4 KB) p8z77v-ifdprog.log (103 KB) p8z77v-ifdprog-rdev.log (446 KB)
Issue #583 has been updated by Bill XIE.
File p8z77v-loop.log added
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2071
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Affected versions: main * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) p8z77-v-pcielane-gpio-probe-map.png (257 KB) p8z77v-r1.02.png (3.09 MB) p8z77v-r1.02-where-to-probe.png (3.09 MB) p8z77v-ifd.bin (4 KB) p8z77v-ifdprog.log (103 KB) p8z77v-ifdprog-rdev.log (446 KB) p8z77v-loop.log (167 KB)
Issue #583 has been updated by Bill XIE.
File dump-me-status.diff added
Dump ME status:
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2072
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Affected versions: main * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) p8z77-v-pcielane-gpio-probe-map.png (257 KB) p8z77v-r1.02.png (3.09 MB) p8z77v-r1.02-where-to-probe.png (3.09 MB) p8z77v-ifd.bin (4 KB) p8z77v-ifdprog.log (103 KB) p8z77v-ifdprog-rdev.log (446 KB) p8z77v-loop.log (167 KB) dump-me-status.diff (1.01 KB)
Issue #583 has been updated by Keith Hui.
File 87334-ifd-updated.log added
Boot log of a successful update on p8z77-v_le_plus, being developed under CB:87334.
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2073
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Affected versions: main * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) p8z77-v-pcielane-gpio-probe-map.png (257 KB) p8z77v-r1.02.png (3.09 MB) p8z77v-r1.02-where-to-probe.png (3.09 MB) p8z77v-ifd.bin (4 KB) p8z77v-ifdprog.log (103 KB) p8z77v-ifdprog-rdev.log (446 KB) p8z77v-loop.log (167 KB) dump-me-status.diff (1.01 KB) 87334-ifd-updated.log (64 KB)
Issue #583 has been updated by Keith Hui.
File inteltool.pciex2.log added File inteltool.pciex4.log added File p8z77v-leplus.pcie2x.nonvme.log added File p8z77v-leplus.pcie2x.nvme.log added File p8z77v-leplus.pcie4x.nonvme.log added File p8z77v-leplus.pcie4x.nvme.log added
Linux kernel 6.12.7 fails to start with no message on p8z77-v_le_plus if PCIEX16_3 set for x4 without a card installed.
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2074
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Affected versions: main * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) p8z77-v-pcielane-gpio-probe-map.png (257 KB) p8z77v-r1.02.png (3.09 MB) p8z77v-r1.02-where-to-probe.png (3.09 MB) p8z77v-ifd.bin (4 KB) p8z77v-ifdprog.log (103 KB) p8z77v-ifdprog-rdev.log (446 KB) p8z77v-loop.log (167 KB) dump-me-status.diff (1.01 KB) 87334-ifd-updated.log (64 KB) inteltool.pciex4.log (1.58 KB) inteltool.pciex2.log (1.58 KB) p8z77v-leplus.pcie2x.nonvme.log (57.5 KB) p8z77v-leplus.pcie2x.nvme.log (65.3 KB) p8z77v-leplus.pcie4x.nonvme.log (57.7 KB) p8z77v-leplus.pcie4x.nvme.log (59.3 KB)
Issue #583 has been updated by Bill XIE.
File gma-pid.diff added File p8z77v-ifdprog-me.log added
IFD programming works under intact ME, but IGD gets disabled with PCI PID becoming 0xffff, observed via the attached patch.
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2076
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Affected versions: main * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) p8z77-v-pcielane-gpio-probe-map.png (257 KB) p8z77v-r1.02.png (3.09 MB) p8z77v-r1.02-where-to-probe.png (3.09 MB) p8z77v-ifd.bin (4 KB) p8z77v-ifdprog.log (103 KB) p8z77v-ifdprog-rdev.log (446 KB) p8z77v-loop.log (167 KB) dump-me-status.diff (1.01 KB) 87334-ifd-updated.log (64 KB) inteltool.pciex4.log (1.58 KB) inteltool.pciex2.log (1.58 KB) p8z77v-leplus.pcie2x.nonvme.log (57.5 KB) p8z77v-leplus.pcie2x.nvme.log (65.3 KB) p8z77v-leplus.pcie4x.nonvme.log (57.7 KB) p8z77v-leplus.pcie4x.nvme.log (59.3 KB) gma-pid.diff (601 Bytes) p8z77v-ifdprog-me.log (194 KB)
Issue #583 has been updated by Bill XIE.
File p8z77v-goodme-2to4.log added
With the other ME image obtained directly from the board, IGD is not disabled, and everything seems to work fine.
---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583#change-2077
* Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Affected versions: main * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061
The technical details have been worked out and implemented as patch CB:85413. However, two issues remain:
1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change.
This issue tracks our progress implementing this feature.
---Files-------------------------------- autoport-p8z77v-gb83fac3e1c74-dirty.tgz (106 KB) cbmem-0-2-7-noPCIEX1_2.log (81.2 KB) p8z77-v-pcielane-gpio-probe-map.png (257 KB) p8z77v-r1.02.png (3.09 MB) p8z77v-r1.02-where-to-probe.png (3.09 MB) p8z77v-ifd.bin (4 KB) p8z77v-ifdprog.log (103 KB) p8z77v-ifdprog-rdev.log (446 KB) p8z77v-loop.log (167 KB) dump-me-status.diff (1.01 KB) 87334-ifd-updated.log (64 KB) inteltool.pciex4.log (1.58 KB) inteltool.pciex2.log (1.58 KB) p8z77v-leplus.pcie2x.nonvme.log (57.5 KB) p8z77v-leplus.pcie2x.nvme.log (65.3 KB) p8z77v-leplus.pcie4x.nonvme.log (57.7 KB) p8z77v-leplus.pcie4x.nvme.log (59.3 KB) gma-pid.diff (601 Bytes) p8z77v-ifdprog-me.log (194 KB) p8z77v-goodme-2to4.log (320 KB)
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Bill XIE -
Keith Hui