[commit] r5458 - in trunk/src/mainboard: . nokia nokia/ip530

[repository service]

Author: uwe
Date: Mon Apr 19 23:21:54 2010
New Revision: 5458
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5458

Log:
Add support for the Nokia IP530.

It's currently its able to run coreboot + seabios + sgabios.

The following hardware works;
        P3
        i440BX  northbridge
        82371   southbridge
        IDE     normal disks + CF

The following hardware doesn't work:
        4x NIC          21143-PD
        2x PCMCIA       PCI1225PDV

Signed-off-by: Marc Bertens 
Acked-by: Uwe Hermann

Added:
   trunk/src/mainboard/nokia/
   trunk/src/mainboard/nokia/Kconfig
   trunk/src/mainboard/nokia/ip530/
   trunk/src/mainboard/nokia/ip530/Kconfig
   trunk/src/mainboard/nokia/ip530/chip.h
   trunk/src/mainboard/nokia/ip530/devicetree.cb
   trunk/src/mainboard/nokia/ip530/irq_tables.c
   trunk/src/mainboard/nokia/ip530/mainboard.c
   trunk/src/mainboard/nokia/ip530/romstage.c
Modified:
   trunk/src/mainboard/Kconfig

Modified: trunk/src/mainboard/Kconfig
==============================================================================
--- trunk/src/mainboard/Kconfig	Mon Apr 19 22:47:29 2010	(r5457)
+++ trunk/src/mainboard/Kconfig	Mon Apr 19 23:21:54 2010	(r5458)
@@ -68,6 +68,8 @@
    bool "NEC"
 config VENDOR_NEWISYS
    bool "Newisys"
+config VENDOR_NOKIA
+	bool "Nokia"
 config VENDOR_NVIDIA
    bool "NVIDIA"
 config VENDOR_OLPC
@@ -273,6 +275,11 @@

config MAINBOARD_VENDOR
    string
+	default "Nokia"
+	depends on VENDOR_NOKIA
+
+config MAINBOARD_VENDOR
+	string
    default "NVIDIA"
    depends on VENDOR_NVIDIA

@@ -398,6 +405,7 @@
 source "src/mainboard/msi/Kconfig"
 source "src/mainboard/nec/Kconfig"
 source "src/mainboard/newisys/Kconfig"
+source "src/mainboard/nokia/Kconfig"
 source "src/mainboard/nvidia/Kconfig"
 source "src/mainboard/olpc/Kconfig"
 source "src/mainboard/pcengines/Kconfig"

Added: trunk/src/mainboard/nokia/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/nokia/Kconfig	Mon Apr 19 23:21:54 2010	(r5458)
@@ -0,0 +1,28 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Marc Bertens 
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_NOKIA
+
+source "src/mainboard/nokia/ip530/Kconfig"
+
+endchoice
+

Added: trunk/src/mainboard/nokia/ip530/Kconfig
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/nokia/ip530/Kconfig	Mon Apr 19 23:21:54 2010	(r5458)
@@ -0,0 +1,52 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Marc Bertens 
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config BOARD_NOKIA_IP530
+	bool "IP530"
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_PGA370
+	select NORTHBRIDGE_INTEL_I440BX
+	select SOUTHBRIDGE_INTEL_I82371EB
+	select SUPERIO_SMSC_SMSCSUPERIO
+	select ROMCC
+	select HAVE_PIRQ_TABLE
+	select UDELAY_TSC
+	select BOARD_ROMSIZE_KB_256
+
+config MAINBOARD_DIR
+	string
+	default nokia/ip530
+	depends on BOARD_NOKIA_IP530
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "IP530"
+	depends on BOARD_NOKIA_IP530
+
+config HAVE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_NOKIA_IP530
+
+config IRQ_SLOT_COUNT
+	int
+	default 6
+	depends on BOARD_NOKIA_IP530
+

Added: trunk/src/mainboard/nokia/ip530/chip.h
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/nokia/ip530/chip.h	Mon Apr 19 23:21:54 2010	(r5458)
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};

Added: trunk/src/mainboard/nokia/ip530/devicetree.cb
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/nokia/ip530/devicetree.cb	Mon Apr 19 23:21:54 2010	(r5458)
@@ -0,0 +1,94 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Marc Bertens 
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/socket_PGA370	# CPU
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+        chip superio/smsc/smscsuperio	# Super I/O (SMSC FDC37C878)
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.3 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 4
+          end
+          device pnp 3f0.4 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.5 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.7 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.9 on		# Game port
+            io 0x60 = 0x201
+          end
+          device pnp 3f0.a on		# Power-management events (PME)
+            io 0x60 = 0x600
+          end
+          device pnp 3f0.b on		# MIDI port (MPU-401)
+            io 0x60 = 0x330
+            irq 0x70 = 5
+          end
+        end
+      end
+      device pci 7.1 on end		# IDE
+      device pci 7.2 on end		# USB
+      device pci 7.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+    device pci 0d.0 on end		# NIC (DEC DECchip 21142/43)
+    device pci 0e.0 on end		# NIC (DEC DECchip 21142/43)
+    device pci 0f.0 on end		# CardBus bridge (TI PCI1225)
+    device pci 0f.1 on end		# CardBus bridge (TI PCI1225)
+  end
+  device pci_domain 1 on		# PCI domain 1
+    device pci 00.0 on end		# PCI bridge (DEC DECchip 21150)
+  end
+  device pci_domain 2 on		# PCI domain 2
+    device pci 04.0 on end		# NIC (DECchip 21142/43)
+    device pci 04.0 on end		# NIC (DECchip 21142/43)
+  end
+end
+

Added: trunk/src/mainboard/nokia/ip530/irq_tables.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/nokia/ip530/irq_tables.c	Mon Apr 19 23:21:54 2010	(r5458)
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_VERSION,		/* u16 version */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x07 << 3) | 0x0,	/* Interrupt router dev */
+	0,			/* IRQs devoted exclusively to PCI usage */
+	0x8086,			/* Vendor */
+	0x122e,			/* Device */
+	0,			/* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x36,			/* Checksum */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x07 << 3) | 0x0, {{0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x63, 0x0ea8}}, 0x0, 0x0},
+		{0x00, (0x0c << 3) | 0x0, {{0x61, 0x06a8}, {0x62, 0x06a8}, {0x00, 0x06a8}, {0x00, 0x06a8}}, 0x0, 0x0},
+		{0x00, (0x0d << 3) | 0x0, {{0x60, 0x0ea8}, {0x61, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x1, 0x0},
+		{0x00, (0x09 << 3) | 0x0, {{0x62, 0x0ea8}, {0x63, 0x0ea8}, {0x60, 0x0ea8}, {0x61, 0x0ea8}}, 0x2, 0x0},
+		{0x00, (0x0a << 3) | 0x0, {{0x63, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
+		{0x01, (0x00 << 3) | 0x0, {{0x60, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}

Added: trunk/src/mainboard/nokia/ip530/mainboard.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/nokia/ip530/mainboard.c	Mon Apr 19 23:21:54 2010	(r5458)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("Nokia IP530 Mainboard")
+};

Added: trunk/src/mainboard/nokia/ip530/romstage.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ trunk/src/mainboard/nokia/ip530/romstage.c	Mon Apr 19 23:21:54 2010	(r5458)
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include <stdlib.h>
+#include "pc80/serial.c"
+#include "console/console.c"
+#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
+#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
+#include "northbridge/intel/i440bx/raminit.h"
+#include "lib/debug.c"
+#include "pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+
+#define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1)
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/i440bx/raminit.c"
+#include "northbridge/intel/i440bx/debug.c"
+
+static void main(unsigned long bist)
+{
+	if (bist == 0)
+		early_mtrr_init();
+
+	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	uart_init();
+	console_init();
+	report_bist_failure(bist);
+
+	/* Enable access to the full ROM chip, needed very early by CBFS. */
+	i82371eb_enable_rom(PCI_DEV(0, 7, 0) ); /* ISA bridge at 00:07.0. */
+
+	enable_smbus();
+	/* dump_spd_registers(); */
+	sdram_set_registers();
+	sdram_set_spd_registers();
+	sdram_enable();
+	/* ram_check(0, 640 * 1024); */
+}

[commit] r5458 ...

[Stefan Reinauer]

On 4/19/10 11:21 PM, repository service wrote:
> The following hardware doesn't work:
>         4x NIC          21143-PD
>         2x PCMCIA       PCI1225PDV

No surprise.. there seems to be no mptable and a possibly incomplete
pirq table.
> device pci 0d.0 on end		# NIC (DEC DECchip 21142/43)
> device pci 0e.0 on end		# NIC (DEC DECchip 21142/43)
> device pci 0f.0 on end		# CardBus bridge (TI PCI1225)
> device pci 0f.1 on end		# CardBus bridge (TI PCI1225)

These should go away
> end
> device pci_domain 1 on		# PCI domain 1
> device pci 00.0 on end		# PCI bridge (DEC DECchip 21150)
> end
> device pci_domain 2 on		# PCI domain 2
> device pci 04.0 on end		# NIC (DECchip 21142/43)
> device pci 04.0 on end		# NIC (DECchip 21142/43)
> end
>
> +end

This is definitely wrong.. There's only one PCI domain on the 440bx. (on
all x86 systems without MMCONFIG actually)
Also, plugin cards and cards without "drivers" in coreboot don't need to
be mentioned in devicetree.cb (and shouldn't!)
> /* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
> {0x00, (0x07 << 3) | 0x0, {{0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x63, 0x0ea8}}, 0x0, 0x0},
> {0x00, (0x0c << 3) | 0x0, {{0x61, 0x06a8}, {0x62, 0x06a8}, {0x00, 0x06a8}, {0x00, 0x06a8}}, 0x0, 0x0},
> {0x00, (0x0d << 3) | 0x0, {{0x60, 0x0ea8}, {0x61, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x1, 0x0},
> {0x00, (0x09 << 3) | 0x0, {{0x62, 0x0ea8}, {0x63, 0x0ea8}, {0x60, 0x0ea8}, {0x61, 0x0ea8}}, 0x2, 0x0},
> {0x00, (0x0a << 3) | 0x0, {{0x63, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
> {0x01, (0x00 << 3) | 0x0, {{0x60, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},

Which devices are this? Adding a comment might make it easier to fix it.
Also, I think you need to have an mptable _or_ program the 8259 and the
PCI devices' interrupt registers in order to get interrupts working.

Stefan

[commit] r5458 ...

[Peter Stuge]

Stefan Reinauer wrote:
> > device pci_domain 1 on		# PCI domain 1
> > device pci 00.0 on end		# PCI bridge (DEC DECchip 21150)
> > end
> > device pci_domain 2 on		# PCI domain 2
> > device pci 04.0 on end		# NIC (DECchip 21142/43)
> > device pci 04.0 on end		# NIC (DECchip 21142/43)
> > end
> >
> > +end
>
> This is definitely wrong.. There's only one PCI domain on the 440bx.

Note that pci_domain != PCI bus.

I guess those chips are behind some PCI-PCI bridge, but all that
should be detected automatically by coreboot.

//Peter