New patch to review for coreboot: a8f0e55 PCH: Add register descriptions used by IGD OpRegion

[Stefan Reinauer]

Stefan Reinauer ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1751

-gerrit

commit a8f0e5578dbe5d30a5d8caceafa6823f57d17d0a
Author: Stefan Reinauer 
Date:   Wed Sep 19 10:49:12 2012 -0700

PCH: Add register descriptions used by IGD OpRegion

These bits are used by the IGD OpRegion code

Change-Id: I89a11fc5021d51e0c1675ba56f6a3bc3b79bb8aa
    Signed-off-by: Stefan Reinauer 
---
 src/southbridge/intel/bd82x6x/pch.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index c9044ed..8481554 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -472,6 +472,7 @@ int smbus_read_byte(unsigned device, unsigned address);
 #define GPE0_EN		0x28
 #define   PME_B0_EN	(1 << 13)
 #define   PME_EN	(1 << 11)
+#define   TCOSCI_EN	(1 << 6)
 #define SMI_EN		0x30
 #define   INTEL_USB2_EN	 (1 << 18) // Intel-Specific USB2 SMI logic
 #define   LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
@@ -494,6 +495,7 @@ int smbus_read_byte(unsigned device, unsigned address);
 #define SS_CNT		0x50
 #define C3_RES		0x54
 #define TCO1_STS	0x64
+#define   DMISCI_STS	(1 << 9)
 #define TCO2_STS	0x66

/*