Patch set updated for coreboot: 850fd7a Intel CPUs: Fix counting of CPU cores

[Kyösti Mälkki]

Kyösti Mälkki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1172

-gerrit

commit 850fd7a8379c49ec961dda12c8119f405c0d3cec
Author: Kyösti Mälkki 
Date:   Wed Jul 4 12:02:58 2012 +0300

Intel CPUs: Fix counting of CPU cores

Detection for a hyper-threading CPU was not compatible with multicore
    CPUs. When using CPUID eax==4, also need to set ecx=0.

CAR init tested on real hardware with hyper-threading model_f25 and
    under qemu 0.15.1 with multicore CPU.

Change-Id: I28ac8790f94652e4ba8ff88fe7812c812f967608
    Signed-off-by: Kyösti Mälkki 
---
 src/cpu/intel/car/cache_as_ram_ht.inc        |   34 ++++++++++++++++++++-----
 src/cpu/intel/hyperthreading/intel_sibling.c |    7 ++++-
 2 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 65da516..2a8d854 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -127,16 +127,36 @@ bsp_init:

post_code(0x24)

-	/* For a hyper-threading processor, cache must not be disabled
-	 * on an AP on the same physical package with the BSP.
-	 */
-	movl	$01, %eax
+	movl	$1, %eax
    cpuid
    btl	$28, %edx
    jnc	sipi_complete
    bswapl	%ebx
-	cmpb	$01, %bh
-	jbe	sipi_complete
+	movzx	%bh, %edi
+	cmpb	$1, %bh
+	jbe	sipi_complete	/* only one LAPIC ID in package */
+
+	movl	$0, %eax
+	cpuid
+	movb	$1, %bl
+	cmpl	$4, %eax
+	jb	cores_counted
+	movl	$4, %eax
+	movl	$0, %ecx
+	cpuid
+	shr	$26, %eax
+	movb	%al, %bl
+	inc	%bl
+
+cores_counted:
+	movl	%edi, %eax
+	divb	%bl
+	cmpb	$1, %al
+	jbe	sipi_complete	/* only LAPIC ID of a core */
+
+	/* For a hyper-threading processor, cache must not be disabled
+	 * on an AP on the same physical package with the BSP.
+	 */

hyper_threading_cpu:

@@ -202,7 +222,7 @@ ap_init:
 ap_halt:
    cli
 1:	hlt
-	jnz	1b
+	jmp	1b

diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
index b9a9ae7..f30ea45 100644
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -28,8 +28,11 @@ int intel_ht_sibling(void)
    	apic_ids = 1;

core_ids = 1;
-	if (cpuid_eax(0) >= 4)
-		core_ids += (cpuid_eax(4) >> 26) & 0x3f;
+	if (cpuid_eax(0) >= 4) {
+		struct cpuid_result result;
+		result = cpuid_ext(4, 0);
+		core_ids += (result.eax >> 26) & 0x3f;
+	}

threads = (apic_ids / core_ids);
    return !!(lapicid() & (threads-1));