New patch to review for coreboot: 8f8d773 libpayload: Add definitions for more config space registers.
Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1735
-gerrit
commit 8f8d773ad06586579f909c207b523effdead3e8a Author: Gabe Black gabeblack@google.com Date: Mon Oct 8 01:56:54 2012 -0700
libpayload: Add definitions for more config space registers.
Change-Id: I02cf353ce7c955cb11ca11c0d5b8aa630cf15fdb Signed-off-by: Gabe Black gabeblack@google.com --- payloads/libpayload/include/pci.h | 61 ++++++++++++++++++++++++++++++++------- 1 file changed, 51 insertions(+), 10 deletions(-)
diff --git a/payloads/libpayload/include/pci.h b/payloads/libpayload/include/pci.h index 005634a..ff07d5c 100644 --- a/payloads/libpayload/include/pci.h +++ b/payloads/libpayload/include/pci.h @@ -34,21 +34,62 @@ #include <arch/types.h> typedef u32 pcidev_t;
-#define REG_VENDOR_ID 0x00 -#define REG_COMMAND 0x04 -#define REG_CLASS_DEV 0x0A -#define REG_HEADER_TYPE 0x0E -#define REG_PRIMARY_BUS 0x18 -#define REG_SUBSYS_VENDOR_ID 0x2C -#define REG_SUBSYS_ID 0x2E +/* Device config space registers. */ +#define REG_VENDOR_ID 0x00 +#define REG_DEVICE_ID 0x02 +#define REG_COMMAND 0x04 +#define REG_STATUS 0x06 +#define REG_REVISION_ID 0x08 +#define REG_PROG_IF 0x09 +#define REG_SUBCLASS 0x0A +#define REG_CLASS 0x0B +#define REG_CACHE_LINE_SIZE 0x0C +#define REG_LATENCY_TIMER 0x0D +#define REG_HEADER_TYPE 0x0E +#define REG_BIST 0x0F +#define REG_BAR0 0x10 +#define REG_BAR1 0x14 +#define REG_BAR2 0x18 +#define REG_BAR3 0x1C +#define REG_BAR4 0x20 +#define REG_BAR5 0x24 +#define REG_CARDBUS_CIS_POINTER 0x28 +#define REG_SUBSYS_VENDOR_ID 0x2C +#define REG_SUBSYS_ID 0x2E +#define REG_DEV_OPROM_BASE 0x30 +#define REG_CAP_POINTER 0x34 +#define REG_INTERRUPT_LINE 0x3C +#define REG_INTERRUPT_PIN 0x3D +#define REG_MIN_GRANT 0x3E +#define REG_MAX_LATENCY 0x3F + +/* Bridge config space registers. */ +#define REG_PRIMARY_BUS 0x18 +#define REG_SECONDARY_BUS 0x19 +#define REG_SUBORDINATE_BUS 0x1A +#define REG_SECONDARY_LATENCY 0x1B +#define REG_IO_BASE 0x1C +#define REG_IO_LIMIT 0x1D +#define REG_SECONDARY_STATUS 0x1E +#define REG_MEMORY_BASE 0x20 +#define REG_MEMORY_LIMIT 0x22 +#define REG_PREFETCH_MEM_BASE 0x24 +#define REG_PREFETCH_MEM_LIMIT 0x26 +#define REG_PREFETCH_BASE_UPPER 0x28 +#define REG_PREFETCH_LIMIT_UPPER 0x2C +#define REG_IO_BASE_UPPER 0x30 +#define REG_IO_LIMIT_UPPER 0x32 +#define REG_BRIDGE_OPROM_BASE 0x38 +#define REG_BRIDGE_CONTROL 0x3C
#define REG_COMMAND_IO (1 << 0) #define REG_COMMAND_MEM (1 << 1) #define REG_COMMAND_BM (1 << 2)
-#define HEADER_TYPE_NORMAL 0 -#define HEADER_TYPE_BRIDGE 1 -#define HEADER_TYPE_CARDBUS 2 +#define HEADER_TYPE_NORMAL 0 +#define HEADER_TYPE_BRIDGE 1 +#define HEADER_TYPE_CARDBUS 2 +#define HEADER_TYPE_MULTIFUNCTION 0x80
#define PCI_ADDR(_bus, _dev, _fn, _reg) \ (0x80000000 | (_bus << 16) | (_dev << 11) | (_fn << 8) | (_reg & ~3))
-
Stefan Reinauer