Hello,
I have a platform (Advantech NAMB-3250MB, used in some Riverbed appliances) which uses Sandy/Ivy Bridge CPUs, but has a DH89xxCC southbridge which according to ifdtool is Ibex Peak. [3]
The ME firmware version from the vendor firmware is 6.0.50.1244 which also corresponds to Ibex Peak (Series 5) and not Cougar Point (Series 6). [1]
I did not know it was possible to pair a Series 5 chipset with Sandy/Ivy Bridge, since the DH89xxCC only supports DMI 1 (intel-communications-chipset-89xx-series-datasheet.pdf page 5) and Sandy/Ivy Bridge support DMI 2.0 [2]
It would appear that using northbridge/intel/sandybridge with southbridge/intel/ibexpeak in coreboot is not supported: /opt/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/romstage/northbridge/intel/sandybridge/early_dmi.o: in function `early_init_dmi': /opt/coreboot/src/northbridge/intel/sandybridge/early_dmi.c:175: undefined reference to `early_pch_init_native_dmi_pre' /opt/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: /opt/coreboot/src/northbridge/intel/sandybridge/early_dmi.c:215: undefined reference to `early_pch_init_native_dmi_post' /opt/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/romstage/northbridge/intel/sandybridge/raminit.o: in function `init_dram_ddr3': /opt/coreboot/src/northbridge/intel/sandybridge/raminit.c:322: undefined reference to `early_pch_init_native' src/arch/x86/Makefile.inc:185: recipe for target 'build/cbfs/fallback/romstage.debug' failed make: *** [build/cbfs/fallback/romstage.debug] Error 1
There is no early_pch_init_native_* in src/southbridge/intel/ibexpeak
Is it safe to assume that IronLake northbridge is not applicable to Sandy/Ivy Bridge CPUs?
In which case, I guess the only way this platform could ever be supported is if the missing early_pch_init_native_* functions are implemented for IbexPeak?
Kind regards, Hal Martin
[1] https://en.wikichip.org/wiki/intel/management_engine
[2] https://www.intel.com/content/www/us/en/products/platforms/details/crystal-f...
[3] ./ifdtool dump.bin PCH Revision: 5 series Ibex Peak FLMAP0: 0x02040002 NR: 2 FRBA: 0x40 NC: 1 FCBA: 0x20 FLMAP1: 0x10100206 ISL: 0x10 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00000120 PSL: 0x0001 FMSBA: 0x200 FLUMAP1: 0x000002ef Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000ef0
ME VSCC table: JID0: 0x004b25bf SPI Component Vendor ID: 0xbf SPI Component Device ID 0: 0x25 SPI Component Device ID 1: 0x4b VSCC0: 0x20092009 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: Yes Lower Write Granularity: 1 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: Yes Upper Write Granularity: 1 bytes Upper Block / Sector Erase Size: 4KB
OEM Section: 00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
Found Region Section FLREG0: 0x00000000 Flash Region 0 (Flash Descriptor): 00000000 - 00000fff FLREG1: 0x07ff0400 Flash Region 1 (BIOS): 00400000 - 007fffff FLREG2: 0x03ff0001 Flash Region 2 (Intel ME): 00001000 - 003fffff FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
Found Component Section FLCOMP 0x0010001c Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 20MHz Write/Erase Clock Frequency: 20MHz Fast Read Clock Frequency: 20MHz Fast Read Support: supported Read Clock Frequency: 20MHz Component 2 Density: 4MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000
Found PCH Strap Section PCHSTRP0 : 0x00205602 PCHSTRP1 : 0x0000010f PCHSTRP2 : 0x90000000 PCHSTRP3 : 0x00000000 PCHSTRP4 : 0x00c8e000 PCHSTRP5 : 0x00000000 PCHSTRP6 : 0x00000000 PCHSTRP7 : 0x00000000 PCHSTRP8 : 0x00000000 PCHSTRP9 : 0x00000000 PCHSTRP10 : 0x00010044 PCHSTRP11 : 0x99000097 PCHSTRP12 : 0x00000000 PCHSTRP13 : 0x00000000 PCHSTRP14 : 0x00000000 PCHSTRP15 : 0x0000000e AltMeDisable bit is not set
Found Master Section FLMSTR1: 0xffff0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000
FLMSTR2: 0xffff0000 (Intel ME) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000
FLMSTR3: 0xffff0118 (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0118
Found Processor Strap Section ????: 0x00000000 ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff
You're looking at a communications platform where the PCH is actually something called Cave Creek or Coleto Creek (depending on the XX number). The DMI for Sandy/Ivy is 'DMI2' but at DMI1 speed, 2.5GT/s.
This PCH is a combination of Ibex Peak (with some IP removed/modified) and the addition of some IP as well as an embedded MAC (on Cave Creek) as it's own PCIe endpoint (meaning communication doesn't go through DMI, you need to have one of the SoCs embedded PCIe lanes connected to it directly.
I worked extensively on these communications platforms when I was with Intel. We paired them with everything. 😊
-----Original Message----- From: Hal Martin hal.martin@gmail.com Sent: Tuesday, July 19, 2022 4:31 PM To: coreboot coreboot@coreboot.org Subject: [coreboot] Intel sandybridge northbridge with ibexpeak southbridge?
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Hello,
I have a platform (Advantech NAMB-3250MB, used in some Riverbed appliances) which uses Sandy/Ivy Bridge CPUs, but has a DH89xxCC southbridge which according to ifdtool is Ibex Peak. [3]
The ME firmware version from the vendor firmware is 6.0.50.1244 which also corresponds to Ibex Peak (Series 5) and not Cougar Point (Series 6). [1]
I did not know it was possible to pair a Series 5 chipset with Sandy/Ivy Bridge, since the DH89xxCC only supports DMI 1 (intel-communications-chipset-89xx- series-datasheet.pdf page 5) and Sandy/Ivy Bridge support DMI 2.0 [2]
It would appear that using northbridge/intel/sandybridge with southbridge/intel/ibexpeak in coreboot is not supported: /opt/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/romstage/northbridge/intel/sandybridge/early_dmi.o: in function `early_init_dmi': /opt/coreboot/src/northbridge/intel/sandybridge/early_dmi.c:175: undefined reference to `early_pch_init_native_dmi_pre' /opt/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: /opt/coreboot/src/northbridge/intel/sandybridge/early_dmi.c:215: undefined reference to `early_pch_init_native_dmi_post' /opt/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/romstage/northbridge/intel/sandybridge/raminit.o: in function `init_dram_ddr3': /opt/coreboot/src/northbridge/intel/sandybridge/raminit.c:322: undefined reference to `early_pch_init_native' src/arch/x86/Makefile.inc:185: recipe for target 'build/cbfs/fallback/romstage.debug' failed make: *** [build/cbfs/fallback/romstage.debug] Error 1
There is no early_pch_init_native_* in src/southbridge/intel/ibexpeak
Is it safe to assume that IronLake northbridge is not applicable to Sandy/Ivy Bridge CPUs?
In which case, I guess the only way this platform could ever be supported is if the missing early_pch_init_native_* functions are implemented for IbexPeak?
Kind regards, Hal Martin
[1] https://en.wikichip.org/wiki/intel/management_engine
[2] https://www.intel.com/content/www/us/en/products/platforms/details/crystal -forest.html?s=Newest
[3] ./ifdtool dump.bin PCH Revision: 5 series Ibex Peak FLMAP0: 0x02040002 NR: 2 FRBA: 0x40 NC: 1 FCBA: 0x20 FLMAP1: 0x10100206 ISL: 0x10 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00000120 PSL: 0x0001 FMSBA: 0x200 FLUMAP1: 0x000002ef Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000ef0
ME VSCC table: JID0: 0x004b25bf SPI Component Vendor ID: 0xbf SPI Component Device ID 0: 0x25 SPI Component Device ID 1: 0x4b VSCC0: 0x20092009 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: Yes Lower Write Granularity: 1 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: Yes Upper Write Granularity: 1 bytes Upper Block / Sector Erase Size: 4KB
OEM Section: 00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
Found Region Section FLREG0: 0x00000000 Flash Region 0 (Flash Descriptor): 00000000 - 00000fff FLREG1: 0x07ff0400 Flash Region 1 (BIOS): 00400000 - 007fffff FLREG2: 0x03ff0001 Flash Region 2 (Intel ME): 00001000 - 003fffff FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
Found Component Section FLCOMP 0x0010001c Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 20MHz Write/Erase Clock Frequency: 20MHz Fast Read Clock Frequency: 20MHz Fast Read Support: supported Read Clock Frequency: 20MHz Component 2 Density: 4MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000
Found PCH Strap Section PCHSTRP0 : 0x00205602 PCHSTRP1 : 0x0000010f PCHSTRP2 : 0x90000000 PCHSTRP3 : 0x00000000 PCHSTRP4 : 0x00c8e000 PCHSTRP5 : 0x00000000 PCHSTRP6 : 0x00000000 PCHSTRP7 : 0x00000000 PCHSTRP8 : 0x00000000 PCHSTRP9 : 0x00000000 PCHSTRP10 : 0x00010044 PCHSTRP11 : 0x99000097 PCHSTRP12 : 0x00000000 PCHSTRP13 : 0x00000000 PCHSTRP14 : 0x00000000 PCHSTRP15 : 0x0000000e AltMeDisable bit is not set
Found Master Section FLMSTR1: 0xffff0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000
FLMSTR2: 0xffff0000 (Intel ME) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000
FLMSTR3: 0xffff0118 (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0118
Found Processor Strap Section ????: 0x00000000 ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
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Hal Martin -
Jeff Daly