Patch set updated for coreboot: 08500eb Intel cpus: Extend cache to cover complete Flash Device

[Kyösti Mälkki]

Kyösti Mälkki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1146

-gerrit

commit 08500ebe42116adc95bd2db59948e0d6197903fb
Author: Kyösti Mälkki 
Date:   Sat Jun 30 11:41:08 2012 +0300

Intel cpus: Extend cache to cover complete Flash Device

CACHE_ROM_SIZE default is ROM_SIZE, the Flash device size set
    in menuconfig. This fixes a case where 8 MB SPI flash MTRR setup
    would not cover the bottom 4 MB when ramstage is decompressed.

Verify CACHE_ROM_SIZE is power of two.
    One may set CACHE_ROM_SIZE==0 to disable this cache.

Change-Id: Ib2b4ea528a092b96ff954894e60406d64f250783
    Signed-off-by: Kyösti Mälkki 
---
 src/cpu/intel/car/cache_as_ram_ht.inc      |    5 ++---
 src/cpu/intel/model_206ax/cache_as_ram.inc |    6 ++++--
 src/cpu/intel/model_6ex/cache_as_ram.inc   |    8 +++++---
 src/include/cpu/x86/mtrr.h                 |    6 ++++++
 4 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 4e0f391..65da516 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -30,9 +30,6 @@
 #define LAPIC(x)		$(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
 #define START_IPI_VECTOR	((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff)

-/* Base address to cache all of Flash ROM, just below 4GB. */
-#define CACHE_ROM_BASE	((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10)
-
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

@@ -380,6 +377,7 @@ no_msr_11e:
    movl	$(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
    wrmsr

+#if CONFIG_CACHE_ROM_SIZE
    /* Enable caching and Speculative Reads for Flash ROM device. */
    movl	$MTRRphysBase_MSR(1), %ecx
    movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
@@ -389,6 +387,7 @@ no_msr_11e:
    rdmsr
    movl	$(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
    wrmsr
+#endif

post_code(0x39)

diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 33246ff..9a2db37 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -259,17 +259,19 @@ before_romstage:
    movl	$CPU_PHYSMASK_HI, %edx	// 36bit address space
    wrmsr

+#if CONFIG_CACHE_ROM_SIZE
    /* Enable Caching and speculative Reads for the
     * complete ROM now that we actually have RAM.
     */
    movl	$MTRRphysBase_MSR(1), %ecx
-	movl	$(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+	movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
    xorl	%edx, %edx
    wrmsr
    movl	$MTRRphysMask_MSR(1), %ecx
-	movl	$(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax
+	movl	$(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
    movl	$CPU_PHYSMASK_HI, %edx
    wrmsr
+#endif

post_code(0x39)

diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index bdefb21..82a568a 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -191,15 +191,17 @@ clear_mtrrs:
    movl	$CPU_PHYSMASK_HI, %edx
    wrmsr

-	/* Enable caching and Speculative Reads for the last 4MB. */
+#if CONFIG_CACHE_ROM_SIZE
+	/* Enable caching and Speculative Reads for Flash ROM device. */
    movl	$MTRRphysBase_MSR(1), %ecx
-	movl	$(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+	movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
    xorl	%edx, %edx
    wrmsr
    movl	$MTRRphysMask_MSR(1), %ecx
-	movl	$(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax
+	movl	$(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
    movl	$CPU_PHYSMASK_HI, %edx
    wrmsr
+#endif

post_code(0x39)

diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 8b5cc28..58bee04 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -56,6 +56,12 @@ void x86_setup_fixed_mtrrs(void);
 # error "CONFIG_XIP_ROM_SIZE is not a power of 2"
 #endif

+#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE -1)) != 0)
+# error "CONFIG_CACHE_ROM_SIZE is not a power of 2"
+#endif
+
+#define CACHE_ROM_BASE	(((1<<20) - (CONFIG_CACHE_ROM_SIZE>>12))<<12)
+
 #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
 # error "CONFIG_RAMTOP must be a power of 2"
 #endif