Ok, so I tried this specific sequence and it failed.
making region read/write done making region read/write Verifing priq routing tables copy at 0xf0000...failed, f0000=b0 while 87c0=24
Could it be that f0000 is mapped to the flash? I'm trying to figure out whether that is technically possible for a gx1? Could the hardware somehow have a control that maps the 2Mbit flash to that block?
Thanks.
--- ramesh bios ramesh_bios@yahoo.com wrote:
Ok, so I think this means I should:
- Enable writes for F0000h thru F3FFFh (in
gx_setup.inc) using BC_XMAP_3 2. Copy the pirq table to F0000 as in pirq_routing.c:copy_pirq_routing_table 3. Enable read and writes for F0000h thru F3FFFh in pirq_routing.c:verify_copy_pirq_routing_table using BC_XMAP_3
I'll give this a shot when I get some time and see how it goes.
Thanks.
--- "Ronald G. Minnich" rminnich@lanl.gov wrote:
for shadow ram, you need to enable writes to go to ram. Later on, when you are done with a region, you need to enable reads.
So the way you do this: figure out which one is
for
0xf0000. Enable writes (2). At the end of the process, you need to set
(3)
for the area.
And, somebody will have to explain how this fits
in
with the new stuff, as I have not looked at shadow ram setup at all in
V2!
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* ramesh bios ramesh_bios@yahoo.com [050304 05:12]:
Ok, so I tried this specific sequence and it failed.
making region read/write done making region read/write Verifing priq routing tables copy at 0xf0000...failed, f0000=b0 while 87c0=24
Could it be that f0000 is mapped to the flash? I'm trying to figure out whether that is technically possible for a gx1? Could the hardware somehow have a control that maps the 2Mbit flash to that block?
In /dev/bios I've been using the following code to switch between the ram image and the rom image. I don't have the specs at hand, but you should look into the specs of device 0x1078:0x0100
static void cs5530_activate(void) { /* Save modified registers for later reset */ pci_dummy[0]=pci_read(CURRENT,0x52);
/* enable rom write access */ pci_write(CURRENT, 0x52, pci_dummy[0]|0x06);
}
static void cs5530_deactivate(void) { pci_write(CURRENT, 0x52, pci_dummy[0]); }
On Thu, 3 Mar 2005, ramesh bios wrote:
Ok, so I tried this specific sequence and it failed.
making region read/write
nope. you need to make it write-only,
Verifing priq routing tables copy at 0xf0000...failed,
then copy
The make it read-write.
Could it be that f0000 is mapped to the flash?
yes, it's supposed to be!
ron
On Fri, 4 Mar 2005, Ronald G. Minnich wrote:
On Thu, 3 Mar 2005, ramesh bios wrote:
Ok, so I tried this specific sequence and it failed.
making region read/write
nope. you need to make it write-only,
arg, I'm not thinking, we are running out of high memory and then RAM.
So making it read/write should have worked. Blash.
Dump the memory at 0xf0000 BEFORE and AFTER you copy the PIRQ.
ron