The VIA VX800 chipset works with the VT8237S code after adding an entry for the VX800 PCI ID.
Signed-off-by: Arjan Koers 0h3q2rmn2bdb@list.nospam.xutrox.com
Index: chipset_enable.c =================================================================== --- chipset_enable.c (revision 589) +++ chipset_enable.c (working copy) @@ -1028,6 +1028,7 @@ {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x}, {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x}, {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, + {0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},
In case anyone needs information about the VX800 chipset, the VX800 / VX820 Series System Programming Manual can be downloaded from: http://linux.via.com.tw/support/beginDownload.action?eleid=161&fid=241
The tests below were performed on my Jetway NF77-N1G6-LF board with VIA VX800 chipset and VIA Nano CPU. Information about the board can be found at these locations: http://www.jetwaycomputer.com/NF77.html http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=581
# ./flashrom flashrom v0.9.0-r589 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. No operations were specified.
# ./flashrom -r backup-a02.bin flashrom v0.9.0-r589 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. Reading flash... done.
# ./flashrom -E flashrom v0.9.0-r589 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. Erasing flash chip... SUCCESS.
# ./flashrom -w nf77a03.bin flashrom v0.9.0-r589 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Programming page:
COMPLETE.
Acked-by: Bari Ari bari@onelabs.com
if you or someone else attaches it as a patch.
Arjan Koers wrote:
The VIA VX800 chipset works with the VT8237S code after adding an entry for the VX800 PCI ID.
Signed-off-by: Arjan Koers 0h3q2rmn2bdb@list.nospam.xutrox.com
Index: chipset_enable.c
--- chipset_enable.c (revision 589) +++ chipset_enable.c (working copy) @@ -1028,6 +1028,7 @@ {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x}, {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x}, {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
{0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},In case anyone needs information about the VX800 chipset, the VX800 / VX820 Series System Programming Manual can be downloaded from: http://linux.via.com.tw/support/beginDownload.action?eleid=161&fid=241
The tests below were performed on my Jetway NF77-N1G6-LF board with VIA VX800 chipset and VIA Nano CPU. Information about the board can be found at these locations: http://www.jetwaycomputer.com/NF77.html http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=581
# ./flashrom flashrom v0.9.0-r589 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. No operations were specified.
# ./flashrom -r backup-a02.bin flashrom v0.9.0-r589 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. Reading flash... done.
# ./flashrom -E flashrom v0.9.0-r589 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. Erasing flash chip... SUCCESS.
# ./flashrom -w nf77a03.bin flashrom v0.9.0-r589 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Programming page:
COMPLETE.
bari wrote:
Acked-by: Bari Ari bari@onelabs.com
if you or someone else attaches it as a patch.
Thanks. The patch has been attached...
On Sun, Jun 14, 2009 at 10:36:55PM +0200, Arjan Koers wrote:
The VIA VX800 chipset works with the VT8237S code after adding an entry for the VX800 PCI ID.
Signed-off-by: Arjan Koers 0h3q2rmn2bdb@list.nospam.xutrox.com
Thanks, committed in r591.
# ./flashrom -E flashrom v0.9.0-r589 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. Erasing flash chip... SUCCESS.
Just to be really sure exerything works ok...
Please do './flashrom -r empty.dd' and them 'hexdump -C empty.dd', which should return only 0xff bytes.
# ./flashrom -w nf77a03.bin flashrom v0.9.0-r589 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Programming page:
COMPLETE.
And here, please try to write an image consisting of random bytes (if you can recover in case things go wrong), then verify it with -v:
dd if=/dev/urandom of=rnd.dd bs=1024c count=512 ./flashrom -w rnd.dd ./flashrom -v rnd.dd
If this verifies OK we can be sure that all works fine. You can then write your proper BIOS image back to the chip.
Thanks, Uwe.
Uwe Hermann wrote:
On Sun, Jun 14, 2009 at 10:36:55PM +0200, Arjan Koers wrote:
The VIA VX800 chipset works with the VT8237S code after adding an entry for the VX800 PCI ID.
Signed-off-by: Arjan Koers 0h3q2rmn2bdb@list.nospam.xutrox.com
Thanks, committed in r591.
Thanks for applying the patch.
# ./flashrom -E flashrom v0.9.0-r589 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. Erasing flash chip... SUCCESS.
Just to be really sure exerything works ok...
Please do './flashrom -r empty.dd' and them 'hexdump -C empty.dd', which should return only 0xff bytes.
# ./flashrom -E ; ./flashrom -r empty.dd ; hexdump -C empty.dd flashrom v0.9.0-r591 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. Erasing flash chip... SUCCESS. flashrom v0.9.0-r591 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. Reading flash... done. 00000000 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| * 00080000
# ./flashrom -w nf77a03.bin flashrom v0.9.0-r589 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Programming page:
COMPLETE.
And here, please try to write an image consisting of random bytes (if you can recover in case things go wrong), then verify it with -v:
Because of a flashing disaster with the DOS tool that Jetway provided, I'm now the owner of a SPI flash programmer ;-)
dd if=/dev/urandom of=rnd.dd bs=1024c count=512 ./flashrom -w rnd.dd ./flashrom -v rnd.dd
If this verifies OK we can be sure that all works fine. You can then write your proper BIOS image back to the chip.
# dd if=/dev/urandom of=rnd.dd bs=1024c count=512 ; ./flashrom -w rnd.dd ; ./flashrom -v rnd.dd 512+0 records in 512+0 records out 524288 bytes (524 kB) copied, 0.19368 s, 2.7 MB/s flashrom v0.9.0-r591 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Programming page:
COMPLETE. flashrom v0.9.0-r591 No coreboot table found. Found chipset "VIA VX800", enabling flash write... Mapping VT8237S MMIO registers at 0xfed10000, unaligned size 0x70. OK. Calibrating delay loop... OK. Found chip "Winbond W25x40" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED.
Uwe Hermann wrote:
# ./flashrom -E flashrom v0.9.0-r589
..
Erasing flash chip... SUCCESS.
Just to be really sure exerything works ok...
Please do './flashrom -r empty.dd' and them 'hexdump -C empty.dd', which should return only 0xff bytes.
No need, flashrom verifies erase properly since r359 of 2008-12-05.
And here, please try to write an image consisting of random bytes
Or zeroes, but that mostly tests the flash cells, not the writing algorithm. I think any verified write after a successful erase is random enough.
#103 and #106 are also relevant here.
//Peter
-
Arjan Koers -
bari -
Peter Stuge -
Uwe Hermann