Author: uwe Date: 2007-05-14 13:33:41 +0200 (Mon, 14 May 2007) New Revision: 2664
Modified: trunk/LinuxBIOSv2/src/mainboard/amd/norwich/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/amd/norwich/failover.c trunk/LinuxBIOSv2/src/mainboard/amd/norwich/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/amd/norwich/mainboard.c trunk/LinuxBIOSv2/targets/amd/norwich/Config.lb Log: AMD Norwich: minor cosmetic fixes and drop dead code (trivial).
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/LinuxBIOSv2/src/mainboard/amd/norwich/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/norwich/cache_as_ram_auto.c 2007-05-11 19:23:57 UTC (rev 2663) +++ trunk/LinuxBIOSv2/src/mainboard/amd/norwich/cache_as_ram_auto.c 2007-05-14 11:33:41 UTC (rev 2664) @@ -40,7 +40,7 @@ #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c"
-static inline int spd_read_byte(unsigned device, unsigned address) +static inline int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } @@ -50,6 +50,7 @@ #define PLLMSRlo 0x02000030 #define DIMM0 0xA0 #define DIMM1 0xA2 + #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -60,6 +61,7 @@ static void msr_init(void) { msr_t msr; + /* Setup access to the cache for under 1MB. */ msr.hi = 0x24fffc02; msr.lo = 0x1000A000; /* 0-A0000 write back */ @@ -87,12 +89,11 @@ msr.hi = 0x20000000; msr.lo = 0x80fffe0; wrmsr(MSR_GLIU1 + 0x21, msr); - }
static void mb_gpio_init(void) { - /* Early mainboard specific GPIO setup */ + /* Early mainboard specific GPIO setup. */ }
void cache_as_ram_main(void) @@ -108,9 +109,8 @@
cs5536_early_setup();
- /* NOTE: must do this AFTER the early_setup! - * it is counting on some early MSR setup - * for cs5536 + /* Note: must do this AFTER the early_setup! It is counting on some early + * MSR setup for CS5536. */ /* cs5536_disable_internal_uart disable them for now, set them up later... */ cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */ @@ -124,9 +124,9 @@
sdram_initialize(1, memctrl);
- /* Check all of memory */ - /*ram_check(0x00000000, 640*1024); */ + /* Check memory. */ + /* ram_check(0x00000000, 640 * 1024); */
- /* Memory is setup. Return to cache_as_ram.inc and continue to boot */ + /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; }
Modified: trunk/LinuxBIOSv2/src/mainboard/amd/norwich/failover.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/norwich/failover.c 2007-05-11 19:23:57 UTC (rev 2663) +++ trunk/LinuxBIOSv2/src/mainboard/amd/norwich/failover.c 2007-05-14 11:33:41 UTC (rev 2664) @@ -8,24 +8,5 @@
static unsigned long main(unsigned long bist) { -#if 0 - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image": /* outputs */ - :"a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset": /* outputs */ - :"a" (bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: -#endif return bist; }
Modified: trunk/LinuxBIOSv2/src/mainboard/amd/norwich/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/norwich/irq_tables.c 2007-05-11 19:23:57 UTC (rev 2663) +++ trunk/LinuxBIOSv2/src/mainboard/amd/norwich/irq_tables.c 2007-05-14 11:33:41 UTC (rev 2664) @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
#include <arch/pirq_routing.h> @@ -55,7 +55,7 @@ 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */ @@ -75,7 +75,7 @@
pirtable_end = copy_pirq_routing_table(addr);
- /* Set up chipset IRQ steering */ + /* Set up chipset IRQ steering. */ pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA); printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, @@ -86,20 +86,23 @@ pirq_tbl = (struct irq_routing_table *)(addr); num_entries = (pirq_tbl->size - 32) / 16;
- /* Set PCI IRQs */ + /* Set PCI IRQs. */ for (i = 0; i < num_entries; i++) { printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); for (j = 0; j < 4; j++) { printk_debug("INT: %c bitmap: %x ", 'A' + j, pirq_tbl->slots[i].irq[j].bitmap); - for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* finds lsb in bitmap to IRQ# */ + for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in bitmap to IRQ#. */ pirq[j] = k; printk_debug("PIRQ: %d\n", k); } - pci_assign_irqs(pirq_tbl->slots[i].bus, pirq_tbl->slots[i].devfn >> 3, pirq); /* bus, device, slots IRQs for {A,B,C,D} */ + + /* Bus, device, slots IRQs for {A,B,C,D}. */ + pci_assign_irqs(pirq_tbl->slots[i].bus, + pirq_tbl->slots[i].devfn >> 3, pirq); }
- /* put the PIR table in memory and checksum */ + /* Put the PIR table in memory and checksum. */ return pirtable_end; }
Modified: trunk/LinuxBIOSv2/src/mainboard/amd/norwich/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/norwich/mainboard.c 2007-05-11 19:23:57 UTC (rev 2663) +++ trunk/LinuxBIOSv2/src/mainboard/amd/norwich/mainboard.c 2007-05-14 11:33:41 UTC (rev 2664) @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
#include <console/console.h> @@ -26,7 +26,9 @@ #include "../../../southbridge/amd/cs5536/cs5536.h" #include "chip.h"
-/* Print the platform configuration - do before PCI init or it will not work right */ +/* Print the platform configuration - do before PCI init or it will not + * work right. + */ void print_conf(void) { #if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR @@ -34,61 +36,49 @@ unsigned long iol; msr_t msr;
- int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, - CPU_DM_CONFIG0, CPU_RCONF_DEFAULT, - CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF, - CPU_RCONF_E0_FF, - CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END + int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0, + CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, + CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM, + GLCP_DELAY_CONTROLS, GL_END };
- int gliu0_msr_defs[] = - { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE4, - MSR_GLIU0_BASE5, MSR_GLIU0_BASE6, + int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, + MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6, GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM, GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, - MSR_GLIU0_SHADOW, - GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2, - GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3, - GLIU0_IOD_SC_4, GLIU0_IOD_SC_5, + MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, + GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, + GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5, GLIU0_GLD_MSR_COH, GL_END };
- int gliu1_msr_defs[] = - { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3, - MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6, - MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9, - MSR_GLIU1_BASE10, - GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, - MSR_GLIU1_SHADOW, - GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, - GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3, + int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, + MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, + MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, + MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0, + GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW, + GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0, + GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3, GLIU1_GLD_MSR_COH, GL_END };
- int rconf_msr[] = - { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4, - CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END + int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, + CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END };
- int cs5536_msr[] = - { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO, - MDD_PIN_OPT, - MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END + int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, + MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, + MDD_IRQM_PRIM, GL_END };
- int pci_msr[] = - { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF, - GLPCI_E0_FF, - GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR, - GLPCI_SPARE, - GL_END + int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, + GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, + GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END };
- int dma_msr[] = - { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3, - MDD_DMA_SHAD4, - MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8, - MDD_DMA_SHAD9, GL_END + int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, + MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6, + MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END };
printk_debug("---------- CPU ------------\n");
Modified: trunk/LinuxBIOSv2/targets/amd/norwich/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/amd/norwich/Config.lb 2007-05-11 19:23:57 UTC (rev 2663) +++ trunk/LinuxBIOSv2/targets/amd/norwich/Config.lb 2007-05-14 11:33:41 UTC (rev 2664) @@ -1,12 +1,12 @@ -# Config file for the AMD Geode LX/5536 Norwich Platform +# Config file for the AMD Geode LX/5536 Norwich Platform.
target norwich mainboard amd/norwich
-#HACK to get the right tsc support +# HACK to get the right TSC support. option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-# leave 36k for vsa +# Leave 36k for VSA. option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
@@ -26,4 +26,4 @@ payload ../payload.elf end
-buildrom ./norwich.rom ROM_SIZE "fallback" +buildrom ./norwich.rom ROM_SIZE "fallback"
-
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