Re: [coreboot] [PATCH] artecgroup/dbe61: Sync irq_tables with dbe62 code to fix compilation and have a chance of working properly.

[Mart Raudsepp]

> Hi,
>
> On 07.05.2008 23:28, Mart Raudsepp wrote:
> > Here's a patch that fixes DBE61 target compilation by making
> > irq_tables.h
> > take the v3 approach. It might actually work on hardware regarding
> > interrupt setup, but we need to get the raminit to work properly to
> > see...
> > so this is in the name of compilation fix and common sense that as all
> > the
> > IRQ routing is the same in DBE61 and DBE62, that the routing settings in
> > dbe62 code should be fine for dbe61 as well.
>
> Well, if the IRQ routing is the same in DBE61 and DBE62, why do the
> tables differ after your patch?

They differ in the interrupt router and IRQs devoted fields only, as told
in the proposed commit message on top of the attachment together with the
reason. And the vendor/device are AMD instead of NSC I believe. The
interrupt line routing tuples are the same and it makes it compile and not
worse.
What does "IRQs devoted exclusively to PCI usage" value affect?

Mart Raudsepp

[PATCH] artecgroup/dbe61: Sync irq_tables with dbe62 code to fix compilation and have a chance of working properly.

[Carl-Daniel Hailfinger]

Marc/Jordan/Ron,

could you take a look at the question at the end of this mail?

On 08.05.2008 07:39, Mart Raudsepp wrote:
> > On 07.05.2008 23:28, Mart Raudsepp wrote:
> > > Here's a patch that fixes DBE61 target compilation by making
> > > irq_tables.h
> > > take the v3 approach. It might actually work on hardware regarding
> > > interrupt setup, but we need to get the raminit to work properly to
> > > see...
> > > so this is in the name of compilation fix and common sense that as all
> > > the
> > > IRQ routing is the same in DBE61 and DBE62, that the routing settings in
> > > dbe62 code should be fine for dbe61 as well.
> >
> > Well, if the IRQ routing is the same in DBE61 and DBE62, why do the
> > tables differ after your patch?
>
> They differ in the interrupt router and IRQs devoted fields only, as told
> in the proposed commit message on top of the attachment together with the
> reason. And the vendor/device are AMD instead of NSC I believe. The
> interrupt line routing tuples are the same and it makes it compile and not
> worse.

Acked-by: Carl-Daniel Hailfinger
> What does "IRQs devoted exclusively to PCI usage" value affect?

No idea.

Regards,
Carl-Daniel

[PATCH] artecgroup/dbe61: Sync irq_tables with dbe62 code to fix compilation and have a chance of working properly.

[Marc Jones]

Carl-Daniel Hailfinger wrote:
> Marc/Jordan/Ron,
> > What does "IRQs devoted exclusively to PCI usage" value affect?

"PCI Exclusive IRQs: This is an IRQ bitmap that indicates which IRQs are 
devoted exclusively for PCI usage. For example, if IRQ11 is devoted 
exclusively to PCI and cannot be assigned to an ISA device, then bit 11 
of this 16-bit field should be set to 1. If there are no IRQs devoted 
exclusively to PCI, then this value should be 0."

http://www.microsoft.com/whdc/archive/pciirq.mspx

You could put 9,10,11 in there but 0 has always worked fine for Geode. I 
am not sure if the OS does anything with that information.

Marc