New patch to review for coreboot: 70d59ee exynos5250: make lowlevel_init_c.c benign

[David Hendricks]

David Hendricks ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2269

-gerrit

commit 70d59ee5d1679c104df56bd8af28fe7696500d44
Author: David Hendricks 
Date:   Sun Feb 3 18:50:37 2013 -0800

exynos5250: make lowlevel_init_c.c benign

This file has mostly (but not entirely) been replaced by coreboot
    stage files. We'll keep it around for a bit longer as a reference,
    but in the meantime we'll stop compiling it as to avoid comptilation
    issues as we change other parts of the code.

Change-Id: I669fb1e5a1517f35979590957d581bd33df53d29
    Signed-off-by: David Hendricks 
---
 src/cpu/samsung/exynos5250/Makefile.inc      | 3 ---
 src/cpu/samsung/exynos5250/lowlevel_init_c.c | 6 ++++++
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc
index 6eee503..49285e7 100644
--- a/src/cpu/samsung/exynos5250/Makefile.inc
+++ b/src/cpu/samsung/exynos5250/Makefile.inc
@@ -6,7 +6,6 @@
 romstage-y += clock.c
 romstage-y += clock_init.c
 romstage-y += exynos_cache.c
-romstage-y += lowlevel_init_c.c
 romstage-y += pinmux.c
 romstage-y += power.c
 romstage-y += soc.c
@@ -23,7 +22,6 @@ romstage-y += dmc_init_ddr3.c
 ramstage-y += clock.c
 ramstage-y += clock_init.c
 ramstage-y += exynos_cache.c
-ramstage-y += lowlevel_init_c.c
 ramstage-y += pinmux.c
 ramstage-y += power.c
 ramstage-y += soc.c
@@ -31,7 +29,6 @@ ramstage-y += uart.c

#ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c
 #ramstage-$(CONFIG_SATA_AHCI) += sata.c
-ramstage-$(CONFIG_SPL_BUILD) += lowlevel_init_c.c

exynos5250_add_bl1: $(obj)/coreboot.pre
    printf "    DD         Adding Samsung Exynos5250 BL1\n"
diff --git a/src/cpu/samsung/exynos5250/lowlevel_init_c.c b/src/cpu/samsung/exynos5250/lowlevel_init_c.c
index 848ebee..daa691f 100644
--- a/src/cpu/samsung/exynos5250/lowlevel_init_c.c
+++ b/src/cpu/samsung/exynos5250/lowlevel_init_c.c
@@ -23,6 +23,12 @@
  * MA 02111-1307 USA
  */

+/*
+ * FIXME: This file is essentially the "bootblock" leftover from U-Boot. For
+ * now it serves as a reference until all the resume-related stuff is added
+ * to the appropriate bootblock/romstage/ramstage files in coreboot.
+ */
+
 #include <common.h>
 #include <config.h>
 #include <cpu/samsung/exynos5-common/exynos5-common.h>