Hi,
it seems that rs690_htinit() does nothing (it only prints some data). Is that intentional?
The RS690 chipset has a problem where it will not work with 1 GHz HT speed unless NB_CFG_Q_F1000_800 bit 0 is set. I think we could add code for this to rs690_htinit().
/***************************************** * Compliant with CIM_33's ATINB_HTInit * Init HT link speed/width for rs690 -- k8 link *****************************************/ static void rs690_htinit() { /* * About HT, it has been done in enumerate_ht_chain(). */ device_t k8_f0; u32 reg; u8 k8_ht_freq;
k8_f0 = PCI_DEV(0, 0x18, 0); /************************ * get k8's ht freq, in k8's function 0, offset 0x88 * bit11-8, specifics the maximum operation frequency of the link's transmitter clock. * The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero * value to this reg, and that value takes effect on the next warm reset or * LDTSTOP_L disconnect sequence. * 0000b = 200Mhz * 0010b = 400Mhz * 0100b = 600Mhz * 0101b = 800Mhz * 0110b = 1Ghz * 1111b = 1Ghz ************************/ reg = pci_read_config32(k8_f0, 0x88); k8_ht_freq = (reg & 0xf00) >> 8; printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq); }
As you can see, we only read the K8 HT speed.
I have created a patch which tests if the K8 HT speed is 1 GHz and sets NB_CFG_Q_F1000_800 bit 0 in that case.
But this can fail if the processor has more than one HT link. My idea was to look at RS690 HT link configuration instead because it has only one HT link. There is another problem because rs690_htinit() is called before optimize_link_incoherent_ht(). The new link speed is only known after optimize_link_incoherent_ht(). Calling rs690_htinit() too early has no effect.
I call rs690_htinit() again after optimize_link_incoherent_ht().
What do you think?
Regards, Carl-Daniel
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c (Revision 3811) +++ LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c (Arbeitskopie) @@ -175,8 +175,9 @@ /* * About HT, it has been done in enumerate_ht_chain(). */ - device_t k8_f0; + device_t k8_f0, rs690_f0; u32 reg; + u8 reg8; u8 k8_ht_freq;
k8_f0 = PCI_DEV(0, 0x18, 0); @@ -196,6 +197,16 @@ reg = pci_read_config32(k8_f0, 0x88); k8_ht_freq = (reg & 0xf00) >> 8; printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq); + if ((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) { + rs690_f0 = PCI_DEV(0, 0, 0); + reg8 = pci_read_config8(rs690_f0, 0x9c); + printk_info("rs690_ht_init NB_CFG_Q_F1000_800=%x\n", reg8); + if (!(reg8 & 0x1)) { + printk_info("rs690_ht_init setting bit 0 in NB_CFG_Q_F1000_800 to allow 1 GHz HT\n"); + reg8 |= 0x1; + pci_write_config8(rs690_f0, 0x9c, reg8); + } + } }
/******************************************************* Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Revision 3811) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Arbeitskopie) @@ -210,6 +210,7 @@
needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs690_htinit(); printk_debug("needs_reset=0x%x\n", needs_reset);
It is great to remind me that.
I knew this issue when I did the 690 code. The board I worked with seemed to support just 800Mhz HT link, which doesn't need any more setting when HT is set up. Then I ignore this. Then I had to move on.
As a matter of fact, both 600Mhz and 1Ghz have their own specific setting. I thought rs690_htinit should be removed from rs690_early_setup() and called after optimize_link_incoherent_ht().
Zheng (Joe)
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Carl-Daniel Hailfinger Sent: Friday, December 12, 2008 12:25 PM To: Coreboot Subject: [coreboot] RS690 HT init
Hi,
it seems that rs690_htinit() does nothing (it only prints some data). Is that intentional?
The RS690 chipset has a problem where it will not work with 1 GHz HT speed unless NB_CFG_Q_F1000_800 bit 0 is set. I think we could add code for this to rs690_htinit().
/***************************************** * Compliant with CIM_33's ATINB_HTInit * Init HT link speed/width for rs690 -- k8 link *****************************************/ static void rs690_htinit() { /* * About HT, it has been done in enumerate_ht_chain(). */ device_t k8_f0; u32 reg; u8 k8_ht_freq;
k8_f0 = PCI_DEV(0, 0x18, 0); /************************ * get k8's ht freq, in k8's function 0, offset 0x88 * bit11-8, specifics the maximum operation frequency of the link's transmitter clock. * The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero * value to this reg, and that value takes effect on the next warm reset or * LDTSTOP_L disconnect sequence. * 0000b = 200Mhz * 0010b = 400Mhz * 0100b = 600Mhz * 0101b = 800Mhz * 0110b = 1Ghz * 1111b = 1Ghz ************************/ reg = pci_read_config32(k8_f0, 0x88); k8_ht_freq = (reg & 0xf00) >> 8; printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq); }
As you can see, we only read the K8 HT speed.
I have created a patch which tests if the K8 HT speed is 1 GHz and sets NB_CFG_Q_F1000_800 bit 0 in that case.
But this can fail if the processor has more than one HT link. My idea was to look at RS690 HT link configuration instead because it has only one HT link. There is another problem because rs690_htinit() is called before optimize_link_incoherent_ht(). The new link speed is only known after optimize_link_incoherent_ht(). Calling rs690_htinit() too early has no effect.
I call rs690_htinit() again after optimize_link_incoherent_ht().
What do you think?
Regards, Carl-Daniel
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c (Revision 3811) +++ LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c (Arbeitskopie) @@ -175,8 +175,9 @@ /* * About HT, it has been done in enumerate_ht_chain(). */ - device_t k8_f0; + device_t k8_f0, rs690_f0; u32 reg; + u8 reg8; u8 k8_ht_freq;
k8_f0 = PCI_DEV(0, 0x18, 0); @@ -196,6 +197,16 @@ reg = pci_read_config32(k8_f0, 0x88); k8_ht_freq = (reg & 0xf00) >> 8; printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq); + if ((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) { + rs690_f0 = PCI_DEV(0, 0, 0); + reg8 = pci_read_config8(rs690_f0, 0x9c); + printk_info("rs690_ht_init NB_CFG_Q_F1000_800=%x\n", reg8); + if (!(reg8 & 0x1)) { + printk_info("rs690_ht_init setting bit 0 in NB_CFG_Q_F1000_800 to allow 1 GHz HT\n"); + reg8 |= 0x1; + pci_write_config8(rs690_f0, 0x9c, reg8); + } + } }
/******************************************************* Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Revision 3811) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Arbeitskopie) @@ -210,6 +210,7 @@
needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs690_htinit(); printk_debug("needs_reset=0x%x\n", needs_reset);
On 12.12.2008 06:35, Bao, Zheng wrote:
It is great to remind me that.
I knew this issue when I did the 690 code. The board I worked with seemed to support just 800Mhz HT link, which doesn't need any more setting when HT is set up. Then I ignore this. Then I had to move on.
As a matter of fact, both 600Mhz and 1Ghz have their own specific setting. I thought rs690_htinit should be removed from rs690_early_setup() and called after optimize_link_incoherent_ht().
Zheng (Joe)
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Carl-Daniel Hailfinger Sent: Friday, December 12, 2008 12:25 PM To: Coreboot Subject: [coreboot] RS690 HT init
Hi,
it seems that rs690_htinit() does nothing (it only prints some data). Is that intentional?
The RS690 chipset has a problem where it will not work with 1 GHz HT speed unless NB_CFG_Q_F1000_800 bit 0 is set. I think we could add code for this to rs690_htinit().
Handle RS690 quirks for 1 GHz noncoherent HyperTransport.
Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: southbridge/amd/rs690/rs690_early_setup.c =================================================================== --- southbridge/amd/rs690/rs690_early_setup.c (Revision 3837) +++ southbridge/amd/rs690/rs690_early_setup.c (Arbeitskopie) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2008 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -175,8 +176,9 @@ /* * About HT, it has been done in enumerate_ht_chain(). */ - device_t k8_f0; + device_t k8_f0, rs690_f0; u32 reg; + u8 reg8; u8 k8_ht_freq;
k8_f0 = PCI_DEV(0, 0x18, 0); @@ -195,7 +197,22 @@ ************************/ reg = pci_read_config32(k8_f0, 0x88); k8_ht_freq = (reg & 0xf00) >> 8; - printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq); + printk_spew("rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq); + rs690_f0 = PCI_DEV(0, 0, 0); + reg8 = pci_read_config8(rs690_f0, 0x9c); + printk_spew("rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8); + /* For 1000 MHz HT, NB_CFG_Q_F1000_800 bit 0 MUST be set. + * For any other HT frequency, NB_CFG_Q_F1000_800 bit 0 MUST NOT be set. + */ + if (((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) && (!(reg8 & 0x1))) { + printk_info("rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n"); + reg8 |= 0x1; + pci_write_config8(rs690_f0, 0x9c, reg8); + } else if ((k8_ht_freq != 0x6) && (k8_ht_freq != 0xf) && (reg8 & 0x1)) { + printk_info("rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n"); + reg8 &= ~0x1; + pci_write_config8(rs690_f0, 0x9c, reg8); + } }
/******************************************************* @@ -462,7 +479,6 @@ break; }
- rs690_htinit(); k8_optimization(); rs690_por_init(nb_dev); } Index: mainboard/amd/dbm690t/cache_as_ram_auto.c =================================================================== --- mainboard/amd/dbm690t/cache_as_ram_auto.c (Revision 3837) +++ mainboard/amd/dbm690t/cache_as_ram_auto.c (Arbeitskopie) @@ -210,6 +210,7 @@
needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs690_htinit(); printk_debug("needs_reset=0x%x\n", needs_reset);
Index: mainboard/amd/pistachio/cache_as_ram_auto.c =================================================================== --- mainboard/amd/pistachio/cache_as_ram_auto.c (Revision 3837) +++ mainboard/amd/pistachio/cache_as_ram_auto.c (Arbeitskopie) @@ -213,6 +213,7 @@
needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs690_htinit(); printk_debug("needs_reset=0x%x\n", needs_reset);
post_code(0x06);
Carl-Daniel Hailfinger wrote:
Handle RS690 quirks for 1 GHz noncoherent HyperTransport.
Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Acked-by: Peter Stuge peter@stuge.se
It has been tested on dbm690t which HT link works on 800Mhz.
Zheng
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Peter Stuge Sent: Tuesday, December 23, 2008 11:59 AM To: Coreboot Subject: Re: [coreboot] RS690 HT init
Carl-Daniel Hailfinger wrote:
Handle RS690 quirks for 1 GHz noncoherent HyperTransport.
Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor.
Signed-off-by: Carl-Daniel Hailfinger
c-d.hailfinger.devel.2006@gmx.net
Acked-by: Peter Stuge peter@stuge.se
-- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
On 23.12.2008 06:38, Bao, Zheng wrote:
It has been tested on dbm690t which HT link works on 800Mhz.
Zheng
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Peter Stuge Sent: Tuesday, December 23, 2008 11:59 AM To: Coreboot Subject: Re: [coreboot] RS690 HT init
Carl-Daniel Hailfinger wrote:
Handle RS690 quirks for 1 GHz noncoherent HyperTransport.
Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor.
Signed-off-by: Carl-Daniel Hailfinger
c-d.hailfinger.devel.2006@gmx.net
Acked-by: Peter Stuge peter@stuge.se
Thanks, committed in r3839.
Regards, Carl-Daniel
I am not sure about if the NB_CFG_Q_F1000_800 affect the LINK_FREQ_CAP_A. If yes, it will affect the negotiation of HT link. If the HT reset hang is caused by 1Ghz issue, it seems that this 2 things don't have hard relationship.
Zheng
-----Original Message----- From: coreboot-bounces@coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Carl-Daniel Hailfinger Sent: Friday, December 12, 2008 12:25 PM To: Coreboot Subject: [coreboot] RS690 HT init
Hi,
it seems that rs690_htinit() does nothing (it only prints some data). Is that intentional?
The RS690 chipset has a problem where it will not work with 1 GHz HT speed unless NB_CFG_Q_F1000_800 bit 0 is set. I think we could add code for this to rs690_htinit().
/***************************************** * Compliant with CIM_33's ATINB_HTInit * Init HT link speed/width for rs690 -- k8 link *****************************************/ static void rs690_htinit() { /* * About HT, it has been done in enumerate_ht_chain(). */ device_t k8_f0; u32 reg; u8 k8_ht_freq;
k8_f0 = PCI_DEV(0, 0x18, 0); /************************ * get k8's ht freq, in k8's function 0, offset 0x88 * bit11-8, specifics the maximum operation frequency of the link's transmitter clock. * The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero * value to this reg, and that value takes effect on the next warm reset or * LDTSTOP_L disconnect sequence. * 0000b = 200Mhz * 0010b = 400Mhz * 0100b = 600Mhz * 0101b = 800Mhz * 0110b = 1Ghz * 1111b = 1Ghz ************************/ reg = pci_read_config32(k8_f0, 0x88); k8_ht_freq = (reg & 0xf00) >> 8; printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq); }
As you can see, we only read the K8 HT speed.
I have created a patch which tests if the K8 HT speed is 1 GHz and sets NB_CFG_Q_F1000_800 bit 0 in that case.
But this can fail if the processor has more than one HT link. My idea was to look at RS690 HT link configuration instead because it has only one HT link. There is another problem because rs690_htinit() is called before optimize_link_incoherent_ht(). The new link speed is only known after optimize_link_incoherent_ht(). Calling rs690_htinit() too early has no effect.
I call rs690_htinit() again after optimize_link_incoherent_ht().
What do you think?
Regards, Carl-Daniel
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c (Revision 3811) +++ LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_early_setup.c (Arbeitskopie) @@ -175,8 +175,9 @@ /* * About HT, it has been done in enumerate_ht_chain(). */ - device_t k8_f0; + device_t k8_f0, rs690_f0; u32 reg; + u8 reg8; u8 k8_ht_freq;
k8_f0 = PCI_DEV(0, 0x18, 0); @@ -196,6 +197,16 @@ reg = pci_read_config32(k8_f0, 0x88); k8_ht_freq = (reg & 0xf00) >> 8; printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq); + if ((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) { + rs690_f0 = PCI_DEV(0, 0, 0); + reg8 = pci_read_config8(rs690_f0, 0x9c); + printk_info("rs690_ht_init NB_CFG_Q_F1000_800=%x\n", reg8); + if (!(reg8 & 0x1)) { + printk_info("rs690_ht_init setting bit 0 in NB_CFG_Q_F1000_800 to allow 1 GHz HT\n"); + reg8 |= 0x1; + pci_write_config8(rs690_f0, 0x9c, reg8); + } + } }
/******************************************************* Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Revision 3811) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (Arbeitskopie) @@ -210,6 +210,7 @@
needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs690_htinit(); printk_debug("needs_reset=0x%x\n", needs_reset);
-
Bao, Zheng -
Carl-Daniel Hailfinger -
Peter Stuge