Previously when I was testing the jetway target, I found that the IDE devices were always enabled, as the mainboard's Config.lb seems to suggest would be the case.
Today, after running an 'svn up' and reverting the src/southbridge/via/vt8237r to before the breakage in rev 3567, I found that the IDE devices aren't ever enabled, no matter what I set for the values of ide0_enable and ide1_enable in the mainboard's Config.lb. And of course, the board won't boot.
I looked in the built target's image/static.c and found the struct southbridge_via_vt8237r_config with ide0_enable and ide1_enable both set to 1 as they should be.
But back in src/southbridge/via/vt8237r/vt8237r_ide.c (around line 41), sb->ide0_enable and sb->ide1_enable are both 0.
Forcing them to 1 there causes the devices to be enabled, and then the system will boot.
But the question is, what's going on there? Why are these values set to 0? Is ide_init accessing chip_info for the wrong device? Does anyone have any ideas?
-Alex Mauer "hawke"
On Thu, Sep 11, 2008 at 05:20:59PM -0500, Alex Mauer wrote:
But back in src/southbridge/via/vt8237r/vt8237r_ide.c (around line 41), sb->ide0_enable and sb->ide1_enable are both 0.
[...]
But the question is, what's going on there? Why are these values set to 0? Is ide_init accessing chip_info for the wrong device? Does anyone have any ideas?
I had the same problem. I added
device pci f.1 on end # IDE
to the southbridge area of Config.lb and it seemed to resolve the issue.
-Kevin
Kevin O'Connor wrote:
I had the same problem. I added device pci f.1 on end # IDE to the southbridge area of Config.lb and it seemed to resolve the issue.
Yep, that fixed it for me as well. I shouldn't have missed that one...
Attached please find a patch which: * Changes the comment for device f.0 from "IDE" to "SATA" * Turns on the Firewire device a.0 * Turns on the PATA device f.1 * Doesn't turn on the unusable device 10.5, which seems to be built-in vt8237 ethernet.
Signed-off-by: Alex Mauer hawke@hawkesnest.net
Index: src/mainboard/jetway/j7f24/Config.lb =================================================================== --- src/mainboard/jetway/j7f24/Config.lb (revision 3576) +++ src/mainboard/jetway/j7f24/Config.lb (working copy) @@ -97,15 +97,16 @@ # Both cables are 40pin. register "ide0_80pin_cable" = "0" register "ide1_80pin_cable" = "0" - device pci f.0 on end # IDE register "fn_ctrl_lo" = "0x80" register "fn_ctrl_hi" = "0x1d" + device pci a.0 on end # Firewire + device pci f.0 on end # SATA + device pci f.1 on end # IDE device pci 10.0 on end # OHCI device pci 10.1 on end # OHCI device pci 10.2 on end # OHCI device pci 10.3 on end # OHCI device pci 10.4 on end # EHCI - device pci 10.5 on end # UDCI device pci 11.0 on # Southbridge LPC chip superio/fintek/f71805f # Super I/O device pnp 2e.0 off # Floppy
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Alex Mauer -
Kevin O'Connor -
ron minnich