FIRST LINUX BOOT: v3 on alix1c!

[ron minnich]

With this patch to FILO:
Index: i386/timer.c
===================================================================
--- i386/timer.c        (revision 35)
+++ i386/timer.c        (working copy)
@@ -105,7 +105,7 @@
        return (end - start) * CLOCK_TICK_RATE / (1000*LATCH);
 }

-static unsigned long long cpu_khz;
+static unsigned long long cpu_khz = 500000;
 void setup_timers(void)
 {
        if (!cpu_khz) {

I just booted linux. First v3 boot on real hardware.

There are still problems. Linux is quite busy as revealed by a POST
card but we don't seem to get interrupts. Things are not wired
correctly.

I am attaching the console log as I think this is pretty important for v3 :-)

Wow, this was a long haul, but we are very close. Thanks to you all.

thanks

ron

[Peter Stuge]

On Wed, Feb 06, 2008 at 10:52:02PM -0800, ron minnich wrote:
> I just booted linux. First v3 boot on real hardware.

Congratulations!
> There are still problems. Linux is quite busy as revealed by a POST
> card but we don't seem to get interrupts.

They are probably related.
> Wow, this was a long haul, but we are very close. Thanks to you
> all.

Very exciting! :)

//Peter

[ron minnich]

And it just broke again. Something in phase 6 init is not happening
for some reason.

The cs5536 init is not getting called in phase 6. If somebody wants to
look at the last 30 minutes change log and see what I might have done,
be my guest.

Damn. I hope it is something simple. This is getting old.

here is one fix however.

ron

[Carl-Daniel Hailfinger]

On 07.02.2008 08:46, ron minnich wrote:
> And it just broke again. Something in phase 6 init is not happening
> for some reason.
>
> The cs5536 init is not getting called in phase 6. If somebody wants to
> look at the last 30 minutes change log and see what I might have done,
> be my guest.
>
> Damn. I hope it is something simple. This is getting old.
>
> here is one fix however.
>
> ron

A little more verbose changelog would be appreciated.
> This is a subtle problem.
>
> Devices must have constructor struct members to be used.

Same problem in
superio/fintek/f71805f/superio.c
superio/winbond/w83627hf/superio.c
device/pcie_device.c
device/agp_device.c
device/hypertransport.c
device/pci_device.c (twice)
device/pcix_device.c
device/pnp_device.c
device/cardbus_device.c
device/root_device.c
You might want to look though all of them and fix where appropriate.
> Signed-off-by: Ronald G. Minnich

Acked-by: Carl-Daniel Hailfinger

Regards,
Carl-Daniel

[ron minnich]

Committed revision 577.

With a more  verbose note.

thanks

ron

[Stefan Reinauer]

* ron minnich  [080207 08:46]:
> This is a subtle problem.
>
> Devices must have constructor struct members to be used.
>
> static struct device_operations southbridge_ops = {
> .constructor			= default_device_constructor,

Before we start doing this all over the place.

Do we ever want to define devices and compile them in that we don't want
to use?

If not, the default behavior with no constructor defined should be that
the code automatically uses the default device constructor.

[Peter Stuge]

On Thu, Feb 07, 2008 at 09:28:27PM +0100, Stefan Reinauer wrote:
> If not, the default behavior with no constructor defined should be
> that the code automatically uses the default device constructor.

This makes a lot of sense to me.

//Peter

[ron minnich]

On Feb 7, 2008 12:28 PM, Stefan Reinauer  wrote:
> Do we ever want to define devices and compile them in that we don't want
> to use?

That's what I can't figure out. I can't recall why that test is there.

ron

[Stefan Reinauer]

ron minnich wrote:
> On Feb 7, 2008 12:28 PM, Stefan Reinauer  wrote:
> > Do we ever want to define devices and compile them in that we don't want
> > to use?
>
> That's what I can't figure out. I can't recall why that test is there.

That code was heavily restructured. Lets kick the test and use the 
default constructor. If that doesnt work out we can always go back. If 
we have to do those excessive add of standard behavior orgies, something 
must be wrong, so we won't break something that is not broken ;-)

[ron minnich]

On Feb 7, 2008 4:15 PM, Stefan Reinauer  wrote:
> That code was heavily restructured. Lets kick the test and use the
> default constructor. If that doesnt work out we can always go back. If
> we have to do those excessive add of standard behavior orgies, something
> must be wrong, so we won't break something that is not broken ;-)

ok, somebody fix it :-)

I want to get this damned LX booted. It's not totally obvious to me
how I want to fix this.

ron

[ron minnich]

This was easier than I thought :-)

ron

[Carl-Daniel Hailfinger]

On 08.02.2008 02:20, ron minnich wrote:
> This was easier than I thought :-)
>
> ron
>
> Remove the requirement that all ops have a constructor, since many of them 
> just use the default.
>
> Signed-off-by: Ronald G. Minnich

Acked-by: Carl-Daniel Hailfinger

and commited in r579, thanks.

Regards,
Carl-Daniel

[Carl-Daniel Hailfinger]

Hi Ron,

On 07.02.2008 07:52, ron minnich wrote:
> I just booted linux. First v3 boot on real hardware.

CONGRATULATIONS! This is a really great moment in coreboot history.

Regards,
Carl-Daniel

[Marc Jones]

ron minnich wrote:
> With this patch to FILO:
> Index: i386/timer.c
> ===================================================================
> --- i386/timer.c        (revision 35)
> +++ i386/timer.c        (working copy)
> @@ -105,7 +105,7 @@
>         return (end - start) * CLOCK_TICK_RATE / (1000*LATCH);
>  }
>
> -static unsigned long long cpu_khz;
> +static unsigned long long cpu_khz = 500000;
>  void setup_timers(void)
>  {
>         if (!cpu_khz) {
>
> I just booted linux. First v3 boot on real hardware.
>
> There are still problems. Linux is quite busy as revealed by a POST
> card but we don't seem to get interrupts. Things are not wired
> correctly.
>
> I am attaching the console log as I think this is pretty important for v3 :-)
>
> Wow, this was a long haul, but we are very close. Thanks to you all.
>
> thanks
>
> ron

You need good settings for the southbridge in your platform dts. You 
should be able to copy these from v2.

/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
    lpc_serirq_polarity = "0";

/* 0:continuous 1:quiet */
    lpc_serirq_mode = "0";

/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */
    enable_gpio_int_route = "0";

Marc

[ron minnich]

On Feb 7, 2008 11:27 AM, Marc Jones  wrote:
> You need good settings for the southbridge in your platform dts. You
> should be able to copy these from v2.
>
> /* LPC IRQ polarity. Each bit is an IRQ 0-15. */
>     lpc_serirq_polarity = "0";
> /* 0:continuous 1:quiet */
> lpc_serirq_mode = "0";
>
> /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */
> enable_gpio_int_route = "0";

Here are the current defaults (recall that the dts can set defaults)

constructor = "cs5536_constructors";
        pciid = "PCI_VENDOR_ID_AMD,PCI_DEVICE_ID_AMD_CS5536_ISA";

/* Interrupt enables for LPC bus. Each bit is an IRQ 0-15. */
        lpc_serirq_enable = "0";

/* LPC IRQ polarity. Each bit is an IRQ 0-15. */
        lpc_serirq_polarity = "0";

/* 0:continuous 1:quiet */
        lpc_serirq_mode = "0";

/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */
        enable_gpio_int_route = "0";

/* 0:IDE 1:FLASH, if you are using NAND flash instead of IDE drive. */
        enable_ide_nand_flash = "0";

/* IDE: enable CS5536 IDE. There may be a different IDE
controller on board */
        enable_ide = "0";

/* Enable USB Port 4 (0:host 1:device). */
        enable_USBP4_device = "0";

/* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA.
         * See CS5536 - Data Book (pages 380-381).
         */
        enable_USBP4_overcurrent = "0";

/* COM1 settings */
        com1_enable = "0";
        com1_address = "0x3f8";
        com1_irq = "4";

/* COM2 settings */
        com2_enable = "0";
        com2_address = "0x2f8";
        com2_irq = "3";

[Marc Jones]

ron minnich wrote:
> On Feb 7, 2008 11:27 AM, Marc Jones  wrote:
> > You need good settings for the southbridge in your platform dts. You
> > should be able to copy these from v2.
> >
> > /* LPC IRQ polarity. Each bit is an IRQ 0-15. */
> >     lpc_serirq_polarity = "0";
> > /* 0:continuous 1:quiet */
> > lpc_serirq_mode = "0";
> >
> > /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */
> > enable_gpio_int_route = "0";
>
> Here are the current defaults (recall that the dts can set defaults)
>     constructor = "cs5536_constructors";
>     pciid = "PCI_VENDOR_ID_AMD,PCI_DEVICE_ID_AMD_CS5536_ISA";
>
>     /* Interrupt enables for LPC bus. Each bit is an IRQ 0-15. */
>     lpc_serirq_enable = "0";
>
>     /* LPC IRQ polarity. Each bit is an IRQ 0-15. */
>     lpc_serirq_polarity = "0";
>
>     /* 0:continuous 1:quiet */
>     lpc_serirq_mode = "0";
>
>     /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */
>     enable_gpio_int_route = "0";
>
>     /* 0:IDE 1:FLASH, if you are using NAND flash instead of IDE drive. */
>     enable_ide_nand_flash = "0";
>
>     /* IDE: enable CS5536 IDE. There may be a different IDE
>
> controller on board */
>         enable_ide = "0";
>     /* Enable USB Port 4 (0:host 1:device). */
>     enable_USBP4_device = "0";
>
>     /* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA.
>      * See CS5536 - Data Book (pages 380-381).
>      */
>     enable_USBP4_overcurrent = "0";
>
>     /* COM1 settings */
>     com1_enable = "0";
>     com1_address = "0x3f8";
>     com1_irq = "4";
>
>     /* COM2 settings */
>     com2_enable = "0";
>     com2_address = "0x2f8";
>     com2_irq = "3";

Right, so the defaults of 0 would be bad. You need to match the v2 
mainboard config.lb for your v3 mainboard dts.
for the alixc1 it should be something like this.

southbridge {
            /config/("southbridge/amd/cs5536/dts");
            pcipath = "0xf,0";
            enabled;
            enable_ide = "1";         
            lpc_serirq_enable = "0x000010da";             /* Interrupt 
enables for LPC bus. Each bit is an IRQ 0-15. */
            lpc_serirq_polarity = "0x0000EF25";           /* LPC IRQ 
polarity. Each bit is an IRQ 0-15. */
            lpc_serirq_mode = "1";                                /* 
0:continuous 1:quiet */
            enable_gpio_int_route = "0x0D0C0700";     /* GPIO(0-0x20) 
for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */
        };

Marc