(no subject)

[Marc Bertens]

Hi all,

Here is my svn diff for the Nokia IP530, currently its able to run
coreboot + seabios + sgabios.

The following hardware works;
    P3
    i440BX	northbridge
    82371	southbridge
    IDE	normal disks + CF
    
The following hardware does'nt work:
    4x NIC 		21143-PD
    2x PCMCIA 	PCI1225PDV

For flashing the the bios you need the following patches from patchwork
    http://patchwork.coreboot.org/patch/1185/
    	Intel 28F004/28F400 support
    http://patchwork.coreboot.org/patch/1195/
    	[v2,compilable] Board enable for IP530

I will work on the remaining issues, when someone has any good ideas to
tackle the remainder issues that will  be apriciated.

Marc

[Uwe Hermann]

On Sat, Apr 10, 2010 at 01:33:43PM +0200, Marc Bertens wrote:
> Hi all,
>
> Here is my svn diff for the Nokia IP530, currently its able to run
> coreboot + seabios + sgabios.

Thanks! Please post your Signed-off-by for all patches you send, so we
can commit them.

http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure
> Index: src/mainboard/Kconfig
>
> --- src/mainboard/Kconfig	(revision 5355)
> +++ src/mainboard/Kconfig	(working copy)
> @@ -96,6 +96,8 @@
>    bool "VIA"
>  config VENDOR_WINENT
>    bool "Win Enterprises"
> +config VENDOR_NOKIA
> bool "Nokia"
>
> endchoice
>
> @@ -359,6 +361,11 @@
>    default "Win Enterprise"
>    depends on VENDOR_WINENT
>
> +config MAINBOARD_VENDOR
> string
> default "Nokia"
> depends on VENDOR_NOKIA
>
> source "src/mainboard/a-trend/Kconfig"
>  source "src/mainboard/abit/Kconfig"
>  source "src/mainboard/advantech/Kconfig"
> @@ -405,6 +412,7 @@
>  source "src/mainboard/tyan/Kconfig"
>  source "src/mainboard/via/Kconfig"
>  source "src/mainboard/winent/Kconfig"
> +source "src/mainboard/nokia/Kconfig"

Please insert the above entries in alphabetical order respectively
(not as last entries in the lists).
> Index: src/mainboard/nokia/Kconfig
>
> --- src/mainboard/nokia/Kconfig	(revision 0)
> +++ src/mainboard/nokia/Kconfig	(revision 0)
> @@ -0,0 +1,29 @@
> +##
> +## This file is part of the coreboot project.
> +##
> +## Copyright (C) 2010 Marc Bertens 
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +##
>
> +choice
> prompt "Mainboard model"
> depends on VENDOR_NOKIA
> +##source "src/mainboard/nokia/ip330/Kconfig"

This can be dropped, I assume?
> +source "src/mainboard/nokia/ip530/Kconfig"
>
> +endchoice
> Index: src/mainboard/nokia/ip530/Kconfig
>
> --- src/mainboard/nokia/ip530/Kconfig	(revision 0)
> +++ src/mainboard/nokia/ip530/Kconfig	(revision 0)
> @@ -0,0 +1,54 @@
> +##
> +## This file is part of the coreboot project.
> +##
> +## Copyright (C) 2010 Marc Bertens 
> +##
> +## This program is free software; you can redistribute it and/or modify
> +## it under the terms of the GNU General Public License as published by
> +## the Free Software Foundation; either version 2 of the License, or
> +## (at your option) any later version.
> +##
> +## This program is distributed in the hope that it will be useful,
> +## but WITHOUT ANY WARRANTY; without even the implied warranty of
> +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +## GNU General Public License for more details.
> +##
> +## You should have received a copy of the GNU General Public License
> +## along with this program; if not, write to the Free Software
> +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> +##
>
> +config BOARD_NOKIA_IP530
> bool "IP530"
> select ARCH_X86
>
> +##	select CPU_INTEL_SLOT_1
> select CPU_INTEL_SOCKET_PGA370

Is this correct? If it's 440BX chipset it's very likely to be Slot 1.
> select NORTHBRIDGE_INTEL_I440BX
> select SOUTHBRIDGE_INTEL_I82371EB
> +##	select SUPERIO_WINBOND_W83977TF
> select SUPERIO_SMSC_SMSCSUPERIO

This also looks strange. Which Super I/O is actually on the board?
> Index: src/mainboard/nokia/ip530/devicetree.cb
>
> --- src/mainboard/nokia/ip530/devicetree.cb	(revision 0)
> +++ src/mainboard/nokia/ip530/devicetree.cb	(revision 0)
> @@ -0,0 +1,81 @@

Please add the missing license header to this file.
> +chip northbridge/intel/i440bx		# Northbridge
> device apic_cluster 0 on		# APIC cluster
> chip cpu/intel/socket_PGA370		# CPU

Slot 1? See above.
>  device pci 7.2 on	end		# USB
>  device pci 7.3 on end		# ACPI
>  register "ide0_enable" = "1"
>  register "ide1_enable" = "1"
>  register "ide_legacy_enable" = "1"
>  # Enable UDMA/33 for higher speed if your IDE device(s) support it.
>  register "ide0_drive0_udma33_enable" = "0"
>  register "ide0_drive1_udma33_enable" = "0"
>  register "ide1_drive0_udma33_enable" = "0"
>  register "ide1_drive1_udma33_enable" = "0"

I think you can safely set these to "1" too. Actually, we should do this
for all 440BX boards IMHO (per default). If any user should have issues
it's easy enough to set to "0".
> end
> device pci 0d.0 on 		# Ethernet controller: Digital Equipment Corporation DECchip 21142/43 (rev 41)
> end
> device pci 0e.0 on 		# Ethernet controller: Digital Equipment Corporation DECchip 21142/43 (rev 41)
> end
> device pci 0f.0 on 		# CardBus bridge: Texas Instruments PCI1225 (rev 01)
> end
> device pci 0f.1 on 		# CardBus bridge: Texas Instruments PCI1225 (rev 01)
> end
> end
> device pci_domain 1 on		# PCI domain 01
> device pci 00.0 on 		# PCI bridge: Digital Equipment Corporation DECchip 21150 (rev 06) (prog-if 00 [Normal decode])
> end
> end
> device pci_domain 2 on		# PCI domain 02
> device pci 04.0 on 		# Ethernet controller: Digital Equipment Corporation DECchip 21142/43 (rev 41)
> end
> device pci 04.0 on 		# Ethernet controller: Digital Equipment Corporation DECchip 21142/43 (rev 41)
> end
> end

Not sure if this is needed?

Have you posted "lspci -tvnn" of your board somewhere?
> Index: src/mainboard/nokia/ip530/asus_p2b_irq_tables.c
>
> --- src/mainboard/nokia/ip530/asus_p2b_irq_tables.c	(revision 0)
> +++ src/mainboard/nokia/ip530/asus_p2b_irq_tables.c	(revision 0)

This must be renamed to irq_tables.c of course. If it does not fully work
yet, we can either commit it if it partially works, or drop it completely
for now.
> Index: src/mainboard/nokia/ip530/irq_tables.c
>
> --- src/mainboard/nokia/ip530/irq_tables.c	(revision 0)
> +++ src/mainboard/nokia/ip530/irq_tables.c	(revision 0)

Oh, there's an irq_tables.c already, so the above can be dropped I guess.
> @@ -0,0 +1,53 @@
> +const struct irq_routing_table intel_irq_routing_table = {
> PIRQ_SIGNATURE,		/* u32 signature */
> PIRQ_VERSION,		/* u16 version */
> 32 + 16 * 6,		/* Max. number of devices on the bus */

Replace 6 with IRQ_SLOT_COUNT here.

Uwe.

[Marc Bertens]

Signed-off-by: Marc Bertens

Op zaterdag 10-04-2010 om 13:33 uur [tijdzone +0200], schreef Marc
Bertens:
> Hi all,
>
> Here is my svn diff for the Nokia IP530, currently its able to run
> coreboot + seabios + sgabios.
>
> The following hardware works;
>    P3
>    i440BX	northbridge
>    82371	southbridge
>    IDE	normal disks + CF
>
> The following hardware does'nt work:
>    4x NIC 		21143-PD
>    2x PCMCIA 	PCI1225PDV
>
> For flashing the the bios you need the following patches from patchwork
>    http://patchwork.coreboot.org/patch/1185/
>    	Intel 28F004/28F400 support
>    http://patchwork.coreboot.org/patch/1195/
>    	[v2,compilable] Board enable for IP530
>
> I will work on the remaining issues, when someone has any good ideas to
> tackle the remainder issues that will  be apriciated.
>
> Marc
>

[Uwe Hermann]

On Mon, Apr 12, 2010 at 06:32:16AM +0200, Marc Bertens wrote:
> Signed-off-by: Marc Bertens

Thanks, committed in r5458 with some of the changes I mentioned.
Sorry for the delay.

Can you please post lspci -tvnn and some more status info? I'd like
to add a wiki page for the board, similar to this one:

http://www.coreboot.org/ASUS_P2B

Thanks, Uwe.

[Stefan Reinauer]

On 4/19/10 11:34 PM, Uwe Hermann wrote:
> On Mon, Apr 12, 2010 at 06:32:16AM +0200, Marc Bertens wrote:
> > Signed-off-by: Marc Bertens
>
> Thanks, committed in r5458 with some of the changes I mentioned.
> Sorry for the delay.
>
> Can you please post lspci -tvnn and some more status info? I'd like
> to add a wiki page for the board, similar to this one:
>
> http://www.coreboot.org/ASUS_P2B

Just reading that page... it says level 2 cache is not enabled...
However, the cpu driver (model_6xx_init.c) says:

static void model_6xx_init(device_t dev)
{
        /* Turn on caching if we haven't already */
        x86_enable_cache();
        x86_setup_mtrrs(36);
        x86_mtrr_check();

/* Update the microcode */
        intel_update_microcode(microcode_updates);

/* Enable the local cpu apics */
        setup_lapic();
};

So it should be enough to add your CPU to the cpu_table in order to get
L2 cache enabled.

Stefan