MSI 7250 (MCP55 based) pci slots Interrupts problem

[George V. Adamov]

Hi evrybody!
I have already asked once about this problem, but no responce resieved, 
so the question is - are the motherboards ms-7260 amd Gigabyte based on 
MCP 55 truly full functional? I mean devices pluged in their pci slots - 
are they really  operatable?

/*here is the old message, perhaps somebody could give an idea what the 
trouble with pci slots could be*/

MSI MS7250 - MCP 55 based motherboard.  
I have troubles with interrupts of devices plug in PCI slots.

If  I use irq_tables.c with only record for irq router (just like it is
for Gigabyte based on MCP55 and MSI7260 ):

write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8,
0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);

Linux says that no interrupt for pin A assigned for devices in pcis slots.

I grubbed IRQ table with getpir and added records for other devices.
As for pci slots it looks like

/*slot0*/
write_pirq_info(pirq_info, 0x01, ((sbdn+0x00)<<3)|0, 0x80/*80*/, 0x0800,
0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x1, 0x0);
 pirq_info++; slot_num++;

/*slot1*/
 write_pirq_info(pirq_info, 0x01, ((sbdn+0x01)<<3)|0,
0x81/*81*/,/*0x0800*/ 0x0800, 0x00,/*0x0*/ 0x0000, 0x00,/*0x0*/ 0x0000,
0x00, 0x00000, 0x2, 0x0);
 pirq_info++; slot_num++;

/*slot2*/
 write_pirq_info(pirq_info, 0x01, ((sbdn+0x02)<<3)|0, 0x82,/*0x4ca0*/  
0x4c80, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x3, 0x0);

And I also used function pci_assign_irqs - to write irqs from the table
into configuration space of each device

After this the device plug  in  pci slot0 starts up (it was a network
card), but running cat /proc/interrupts - showed strange CPU time for
eth0 (at least 3 orders higher than any other device) it was also easy
to note that system was a bit slow with ethernet card pluged. But at
least card worked ;)

I tried to plug it to slot1 and slot2 - when Linux tried to load module
for the card I got NMI ((((

Any ideas what the trouble is ?

[Carl-Daniel Hailfinger]

Hi,

On 10.04.2008 14:16, George V. Adamov wrote:
> Hi evrybody!
> I have already asked once about this problem, but no responce resieved, 
> so the question is - are the motherboards ms-7260 amd Gigabyte based on 
> MCP 55 truly full functional? I mean devices pluged in their pci slots - 
> are they really  operatable?

This depends a lot on the boards. Unfortunately, there is not public
documentation about MCP55 internals.
> /*here is the old message, perhaps somebody could give an idea what the 
> trouble with pci slots could be*/
>
> MSI MS7250 - MCP 55 based motherboard.  
> I have troubles with interrupts of devices plug in PCI slots.
>
> If  I use irq_tables.c with only record for irq router (just like it is
> for Gigabyte based on MCP55 and MSI7260 ):
>
> write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8,
> 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
>
> Linux says that no interrupt for pin A assigned for devices in pcis slots.
>
> I grubbed IRQ table with getpir and added records for other devices.
> As for pci slots it looks like
>
> /*slot0*/
> write_pirq_info(pirq_info, 0x01, ((sbdn+0x00)<<3)|0, 0x80/*80*/, 0x0800,
> 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x1, 0x0);
>  pirq_info++; slot_num++;
>
> /*slot1*/
>  write_pirq_info(pirq_info, 0x01, ((sbdn+0x01)<<3)|0,
> 0x81/*81*/,/*0x0800*/ 0x0800, 0x00,/*0x0*/ 0x0000, 0x00,/*0x0*/ 0x0000,
> 0x00, 0x00000, 0x2, 0x0);
>  pirq_info++; slot_num++;
>
> /*slot2*/
>  write_pirq_info(pirq_info, 0x01, ((sbdn+0x02)<<3)|0, 0x82,/*0x4ca0*/  
> 0x4c80, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x3, 0x0);
>
> And I also used function pci_assign_irqs - to write irqs from the table
> into configuration space of each device
>
> After this the device plug  in  pci slot0 starts up (it was a network
> card), but running cat /proc/interrupts - showed strange CPU time for
> eth0 (at least 3 orders higher than any other device) it was also easy
> to note that system was a bit slow with ethernet card pluged. But at
> least card worked ;)
>
> I tried to plug it to slot1 and slot2 - when Linux tried to load module
> for the card I got NMI ((((
>
> Any ideas what the trouble is ?

Can you post a full boot log with debugging enabled? Please post a patch
against current svn HEAD as well. That way, we have a chance to help you.

Regards,
Carl-Daniel

[yhlu]

On Thu, Apr 10, 2008 at 6:40 AM, Carl-Daniel Hailfinger
 wrote:
> Hi,
>
> On 10.04.2008 14:16, George V. Adamov wrote:
> > Hi evrybody!
> > I have already asked once about this problem, but no responce resieved,
> > so the question is - are the motherboards ms-7260 amd Gigabyte based on
> > MCP 55 truly full functional? I mean devices pluged in their pci slots -
> > are they really  operatable?
>
> This depends a lot on the boards. Unfortunately, there is not public
>  documentation about MCP55 internals.
> > /*here is the old message, perhaps somebody could give an idea what the
> > trouble with pci slots could be*/
> >
> > MSI MS7250 - MCP 55 based motherboard.
> > I have troubles with interrupts of devices plug in PCI slots.
> >
> > If  I use irq_tables.c with only record for irq router (just like it is
> > for Gigabyte based on MCP55 and MSI7260 ):
> >
> > write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8,
> > 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
> >
> > Linux says that no interrupt for pin A assigned for devices in pcis slots.
> >
> > I grubbed IRQ table with getpir and added records for other devices.
> > As for pci slots it looks like
> >
> > /*slot0*/
> > write_pirq_info(pirq_info, 0x01, ((sbdn+0x00)<<3)|0, 0x80/*80*/, 0x0800,
> > 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x1, 0x0);
> >  pirq_info++; slot_num++;
> >
> > /*slot1*/
> >  write_pirq_info(pirq_info, 0x01, ((sbdn+0x01)<<3)|0,
> > 0x81/*81*/,/*0x0800*/ 0x0800, 0x00,/*0x0*/ 0x0000, 0x00,/*0x0*/ 0x0000,
> > 0x00, 0x00000, 0x2, 0x0);
> >  pirq_info++; slot_num++;
> >
> > /*slot2*/
> >  write_pirq_info(pirq_info, 0x01, ((sbdn+0x02)<<3)|0, 0x82,/*0x4ca0*/
> > 0x4c80, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x3, 0x0);
> >
> > And I also used function pci_assign_irqs - to write irqs from the table
> > into configuration space of each device
> >
> > After this the device plug  in  pci slot0 starts up (it was a network
> > card), but running cat /proc/interrupts - showed strange CPU time for
> > eth0 (at least 3 orders higher than any other device) it was also easy
> > to note that system was a bit slow with ethernet card pluged. But at
> > least card worked ;)
> >
> > I tried to plug it to slot1 and slot2 - when Linux tried to load module
> > for the card I got NMI ((((
> >
> > Any ideas what the trouble is ?
>
> Can you post a full boot log with debugging enabled? Please post a patch
>  against current svn HEAD as well. That way, we have a chance to help you.

please make sure you are using 64bit SMP kernel.

BTW. the irq_tables.c is only used for discovering of peer root bus
other than bus0 when acpi is not there.

YH

YH

[George V. Adamov]

yhlu wrote:
> On Thu, Apr 10, 2008 at 6:40 AM, Carl-Daniel Hailfinger
>  wrote:
> > Hi,
> >
> > On 10.04.2008 14:16, George V. Adamov wrote:
> > > Hi evrybody!
> > > I have already asked once about this problem, but no responce resieved,
> > > so the question is - are the motherboards ms-7260 amd Gigabyte based on
> > > MCP 55 truly full functional? I mean devices pluged in their pci slots -
> > > are they really  operatable?
> >
> > This depends a lot on the boards. Unfortunately, there is not public
> > documentation about MCP55 internals.
> > > /*here is the old message, perhaps somebody could give an idea what the
> > > trouble with pci slots could be*/
> > >
> > > MSI MS7250 - MCP 55 based motherboard.
> > > I have troubles with interrupts of devices plug in PCI slots.
> > >
> > > If  I use irq_tables.c with only record for irq router (just like it is
> > > for Gigabyte based on MCP55 and MSI7260 ):
> > >
> > > write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8,
> > > 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
> > >
> > > Linux says that no interrupt for pin A assigned for devices in pcis slots.
> > >
> > > I grubbed IRQ table with getpir and added records for other devices.
> > > As for pci slots it looks like
> > >
> > > /*slot0*/
> > > write_pirq_info(pirq_info, 0x01, ((sbdn+0x00)<<3)|0, 0x80/*80*/, 0x0800,
> > > 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x1, 0x0);
> > >  pirq_info++; slot_num++;
> > >
> > > /*slot1*/
> > >  write_pirq_info(pirq_info, 0x01, ((sbdn+0x01)<<3)|0,
> > > 0x81/*81*/,/*0x0800*/ 0x0800, 0x00,/*0x0*/ 0x0000, 0x00,/*0x0*/ 0x0000,
> > > 0x00, 0x00000, 0x2, 0x0);
> > >  pirq_info++; slot_num++;
> > >
> > > /*slot2*/
> > >  write_pirq_info(pirq_info, 0x01, ((sbdn+0x02)<<3)|0, 0x82,/*0x4ca0*/
> > > 0x4c80, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x3, 0x0);
> > >
> > > And I also used function pci_assign_irqs - to write irqs from the table
> > > into configuration space of each device
> > >
> > > After this the device plug  in  pci slot0 starts up (it was a network
> > > card), but running cat /proc/interrupts - showed strange CPU time for
> > > eth0 (at least 3 orders higher than any other device) it was also easy
> > > to note that system was a bit slow with ethernet card pluged. But at
> > > least card worked ;)
> > >
> > > I tried to plug it to slot1 and slot2 - when Linux tried to load module
> > > for the card I got NMI ((((
> > >
> > > Any ideas what the trouble is ?
> >
> > Can you post a full boot log with debugging enabled? Please post a patch
> > against current svn HEAD as well. That way, we have a chance to help you.
>
> please make sure you are using 64bit SMP kernel.
>
> BTW. the irq_tables.c is only used for discovering of peer root bus
> other than bus0 when acpi is not there.
>
> YH
>
> YH

Here is the debug I recieve via com port:
There are also some additional messages I needed porting code on MS7250, 
in comments I wrote about a little bug which seemed to me not so serious.

LinuxBIOS-2.0.0_Fallback Thu Mar 20 16:51:56 UTC 2008 starting...
bist==0 cpus inited
*sysinfo range: [000cf000,000cf730)
bsp_apicid=00
core0 started:
setup_coherent_ht_domain()started ap apicid: 01
start_other_cores()SBLink=00
NC node|link=00
begin msr fid, vid 310c12120c0c0202
end msr fid, vid 310c120c0c0c020c
mcp55_num:01
ht reset -

LinuxBIOS-2.0.0_Fallback Thu Mar 20 16:51:56 UTC 2008 starting...
bist==0 cpus inited
*sysinfo range: [000cf000,000cf730)
bsp_apicid=00
core0 started:
setup_coherent_ht_domain()started ap apicid: 01
start_other_cores()SBLink=00
NC node|link=00
begin msr fid, vid 310c120c0c0c020c
end msr fid, vid 310c120c0c0c020c
mcp55_num:01
allow_all_aps_stopfill_mem_ctrlenable_smbus()memreset_setup()sdram_initialize 
- started
Ram1.00
setting up CPU00Ram2.00
sdram_set_spd_registers: starting
activate_spd_rom: nothing needs to be done
DDR2 DIMM FOUND CH0
DDR2 DIMM FOUND CH1
spd_enable_2channels
Enabling dual channel memory
Unbuffered
333Mhz
RAM: 0x00100000 KB
Ram3
\0x09dimm_mask = 00000011
\0x09x4_mask = 00000000
\0x09x16_mask = 00000000
\0x09single_rank_mask = 00000001
\0x09ODC = 00111222
\0x09Addr Timing= 00202220
clock started
Initializing memory: done
Setting variable MTRR 02, base: 0000MB, range: 0400MB, type WB
DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=1a done
DQS Training:DQSPos: 00 done
DQS Training:RcvrEn:Pass2: 00 CTLRMaxDelay=34 done
DQS Training:tsc[00]=000000003f141d3a
DQS Training:tsc[01]=0000000040d045c6
DQS Training:tsc[02]=0000000040d045cf
DQS Training:tsc[03]=000000007aea695f
DQS Training:tsc[04]=000000007c990099
Ram4
sdram_initialize - finished
sdram_initialize
dump_mem: /*I dont know why, but part of a flash rom seemed to be 
shadowed, Fallback image should be located here*/
fffe0000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe0090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
fffe00f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
dump_mem: /*mem after initialization*/
00100000: 78 56 34 12 21 43 65 87 89 67 45 23 32 54 76 98
00100010: 24 58 38 59 24 67 49 30 95 07 49 24 33 87 93 99
00100020: 42 56 38 40 45 52 46 38 63 21 43 29 94 78 06 05
00100030: 45 90 34 12 67 34 72 98 34 76 38 12 23 76 58 34
00100040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100050: ff ff ff ff ff ff ff ff 00 00 00 6f 00 00 00 00
00100060: 00 00 00 00 00 00 00 00 6f 2b 00 00 00 64 ff ff
00100070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100080: fe fe fe fe fe fe fe fe fe fe fe fe fe fe fe fe
00100090: 01 01 01 01 01 01 01 01 85 fe 01 01 01 f4 b4 c1
001000a0: fe fe fe fe fe fe fe fe 00 00 10 7a 10 00 00 00
001000b0: 01 01 01 01 01 01 01 01 c5 fe 01 01 00 f4 94 c1
001000c0: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
001000d0: fe fe fe fe fe fe fe fe 00 00 00 6e 00 00 00 00
001000e0: fe fe fe fe fe fe fe fe fe fe fe fe fe fe fe fe
001000f0: 01 01 01 01 01 01 01 01 c5 fe 01 01 00 fc fc d9
12345678v_esp=000cedec
testx = 5a5a5a5a /*a small test write 0x5a5a5a5a to ram and read it back 
to make sure it really works*/
Copying data from cache to RAM -- switching to use RAM as stack... G 
versionDone
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Copying LinuxBIOS to RAM. -AMD
src=fffa0000 /*here I point directly on unshadowed part of flash chip we 
will copy and use Normal Image*/
dst=00100000
dump_mem: /*dump to make sure I really copy what I need*/
fffa0000: 00 47 02 00 df fe da ff fa 2e 0f 01 15 38 01 10
fffa0010: 00 ea 02 01 b8 18 00 00 8e d8 8e c0 ff f6 ff ff
fffa0020: 8e d0 8e e0 8e e8 b0 13 e6 80 fc 8d 3d 00 60 13
fffa0030: 00 b9 00 a0 04 29 f9 c1 e9 02 31 c0 c1 3e 97 dd
fffa0040: f3 ab 13 47 12 84 45 74 07 15 ef df ee be bc 23
fffa0050: 6a 01 55 89 e5 21 30 a2 11 00 8d 1d a1 55 ff 7f
fffa0060: fb bb 00 04 66 89 d8 89 da 66 ba 5d 89 47 00 89
fffa0070: 57 04 83 c3 06 83 c7 08 81 ff bf ed 6e bb d0 25
fffa0080: 75 e3 85 1d 28 08 b0 fe 6f 89 ec e8 fa 42 dc fd
fffa0090: de 6e 30 b0 ee 0a f4 eb f9 4d eb 72 05 01 eb 6c
fffa00a0: dc dc dc dc 02 eb 66 03 eb 60 04 eb 5a 05 eb 54
fffa00b0: 7f f7 df dc 06 eb 4e 07 eb 48 6a 08 eb 44 90 90
fffa00c0: 0b 09 eb 3c 6a 0a eb 38 37 37 77 37 0b eb 32 05
fffa00d0: 0c eb 2c 0d eb 26 0e eb 20 8f fd dd 63 23 0f eb
fffa00e0: 18 05 10 eb 12 6a 11 eb 0e 11 12 eb 06 6f ff ff
fffa00f0: 77 05 13 eb 00 57 56 55 8d 6c 24 20 55 53 52 51
dump_mem: /*and to make shure memory is zeroed*/
00100000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00100090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
001000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
001000b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
001000c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
001000d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
001000e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
001000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
linxbios_ram.nrv2b length = 0000dd36
linxbios_ram.bin length = 00024700
Jumping to LinuxBIOS.
LinuxBIOS-2.0.0_Normal Thu Mar 20 16:51:40 UTC 2008 booting...
Enumerating buses...
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
PCI: 00:18.3 siblings=1
CPU: APIC: 00 enabled
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] enabled
PCI: 00:00.0 [10de/0369] enabled
PCI: 00:00.0 [10de/0369] enabled next_unitid: 0010
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [10de/0369] enabled
PCI: 00:01.0 [10de/0360] enabled
PCI: 00:01.1 [10de/0368] enabled
PCI: 00:01.2 [10de/036a] enabled
PCI: 00:01.3 [10de/036b] enabled
PCI: 00:02.0 [10de/036c] enabled
PCI: 00:02.1 [10de/036d] enabled
PCI: 00:04.0 [10de/036e] enabled
PCI: 00:05.0 [10de/037f] enabled
PCI: 00:05.1 [10de/037f] enabled
PCI: 00:05.2 [10de/037f] enabled
PCI: 00:06.0 [10de/0370] enabled
PCI: 00:06.1 [10de/0371] enabled
PCI: 00:08.0 [10de/0373] enabled
PCI: 00:09.0 [10de/0373] enabled
PCI: 00:0a.0 [10de/0376] enabled
PCI: 00:0b.0 [10de/0374] enabled
PCI: 00:0c.0 [10de/0374] enabled
PCI: 00:0d.0 [10de/0378] enabled
PCI: 00:0e.0 [10de/0375] enabled
PCI: 00:0f.0 [10de/0377] enabled
PNP: 002e.0 enabled
PNP: 002e.1 disabled
PNP: 002e.2 enabled
PNP: 002e.3 disabled
PNP: 002e.5 enabled
PNP: 002e.6 disabled
PNP: 002e.7 disabled
PNP: 002e.8 disabled
PNP: 002e.9 disabled
PNP: 002e.a enabled
PNP: 002e.b enabled
smbus: PCI: 00:01.1[0]->I2C: 01:50 enabled
smbus: PCI: 00:01.1[0]->I2C: 01:51 enabled
smbus: PCI: 00:01.1[0]->I2C: 01:52 enabled
smbus: PCI: 00:01.1[0]->I2C: 01:53 enabled
smbus: PCI: 00:01.1[0]->I2C: 01:54 enabled
smbus: PCI: 00:01.1[0]->I2C: 01:55 enabled
smbus: PCI: 00:01.1[0]->I2C: 01:56 enabled
smbus: PCI: 00:01.1[0]->I2C: 01:57 enabled
smbus: PCI: 00:01.1[1]->I2C: 02:51 enabled
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [1795/0003] enabled
PCI: 01:01.0 [1172/f012] enabled
PCI: 01:02.0 [1172/f012] enabled
PCI: 01:04.0 [1106/3044] enabled
PCI: pci_scan_bus returning with max=001
PCI: pci_scan_bus for bus 02
Disabling static device: PCI: 02:00.0
PCI: pci_scan_bus returning with max=002
PCI: pci_scan_bus for bus 03
PCI: pci_scan_bus returning with max=003
PCI: pci_scan_bus for bus 04
PCI: pci_scan_bus returning with max=004
PCI: pci_scan_bus for bus 05
Disabling static device: PCI: 05:00.0
PCI: pci_scan_bus returning with max=005
PCI: pci_scan_bus for bus 06
PCI: pci_scan_bus returning with max=006
PCI: pci_scan_bus for bus 07
PCI: 07:00.0 [10de/01d1] enabled
PCI: pci_scan_bus returning with max=007
PCI: pci_scan_bus returning with max=007
PCI: pci_scan_bus returning with max=007
done
Allocating resources...
Reading resources...
PCI: 00:06.0 24 <- [0x00fff00000 - 0x00ffefffff] bus 01 prefmem
PCI: 00:0a.0 1c <- [0x00fffff000 - 0x00ffffefff] bus 02 io
PCI: 00:0a.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] bus 02 prefmem
PCI: 00:0a.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 02 mem
PCI: 00:0b.0 1c <- [0x00fffff000 - 0x00ffffefff] bus 03 io
PCI: 00:0b.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] bus 03 prefmem
PCI: 00:0b.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 03 mem
PCI: 00:0c.0 1c <- [0x00fffff000 - 0x00ffffefff] bus 04 io
PCI: 00:0c.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] bus 04 prefmem
PCI: 00:0c.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 04 mem
PCI: 00:0d.0 1c <- [0x00fffff000 - 0x00ffffefff] bus 05 io
PCI: 00:0d.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] bus 05 prefmem
PCI: 00:0d.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 05 mem
PCI: 00:0e.0 1c <- [0x00fffff000 - 0x00ffffefff] bus 06 io
PCI: 00:0e.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] bus 06 prefmem
PCI: 00:0e.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 06 mem
PCI: 00:0f.0 1c <- [0x00fffff000 - 0x00ffffefff] bus 07 io
Done reading resources.
Allocating VGA resource PCI: 07:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:0f.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Setting resources...
VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000003fff] io <node 0 link 0>
PCI: 00:18.0 1b8 <- [0x00e0000000 - 0x00efffffff] prefmem <node 0 link 0>
PCI: 00:18.0 1b0 <- [0x00f0000000 - 0x00f22fffff] mem <node 0 link 0>

pci_dev_set_resources(struct device *dev)
PCI: 00:01.0 14 <- [0x00f2244000 - 0x00f2244fff] mem
PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] io
PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] irq
PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] drq
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] io
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] irq
PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] irq
PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] io
PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] irq

pci_dev_set_resources(struct device *dev)
PCI: 00:01.1 10 <- [0x0000002c00 - 0x0000002c3f] io
PCI: 00:01.1 20 <- [0x0000002c40 - 0x0000002c7f] io
PCI: 00:01.1 24 <- [0x0000002c80 - 0x0000002cbf] io
PCI: 00:01.1 60 <- [0x0000002000 - 0x00000020ff] io
PCI: 00:01.1 64 <- [0x0000002400 - 0x00000024ff] io
PCI: 00:01.1 68 <- [0x0000002800 - 0x00000028ff] io

pci_dev_set_resources(struct device *dev)
PCI: 00:01.3 10 <- [0x00f2200000 - 0x00f223ffff] mem

pci_dev_set_resources(struct device *dev)
PCI: 00:02.0 10 <- [0x00f2245000 - 0x00f2245fff] mem

pci_dev_set_resources(struct device *dev)
PCI: 00:02.1 10 <- [0x00f224b000 - 0x00f224b0ff] mem

pci_dev_set_resources(struct device *dev)
PCI: 00:04.0 20 <- [0x0000002cc0 - 0x0000002ccf] io

pci_dev_set_resources(struct device *dev)
PCI: 00:05.0 10 <- [0x0000003000 - 0x0000003007] io
PCI: 00:05.0 14 <- [0x0000003080 - 0x0000003083] io
PCI: 00:05.0 18 <- [0x0000003010 - 0x0000003017] io
PCI: 00:05.0 1c <- [0x0000003090 - 0x0000003093] io
PCI: 00:05.0 20 <- [0x0000002cd0 - 0x0000002cdf] io
PCI: 00:05.0 24 <- [0x00f2246000 - 0x00f2246fff] mem

pci_dev_set_resources(struct device *dev)
PCI: 00:05.1 10 <- [0x0000003020 - 0x0000003027] io
PCI: 00:05.1 14 <- [0x00000030a0 - 0x00000030a3] io
PCI: 00:05.1 18 <- [0x0000003030 - 0x0000003037] io
PCI: 00:05.1 1c <- [0x00000030b0 - 0x00000030b3] io
PCI: 00:05.1 20 <- [0x0000002ce0 - 0x0000002cef] io
PCI: 00:05.1 24 <- [0x00f2247000 - 0x00f2247fff] mem

pci_dev_set_resources(struct device *dev)
PCI: 00:05.2 10 <- [0x0000003040 - 0x0000003047] io
PCI: 00:05.2 14 <- [0x00000030c0 - 0x00000030c3] io
PCI: 00:05.2 18 <- [0x0000003050 - 0x0000003057] io
PCI: 00:05.2 1c <- [0x00000030d0 - 0x00000030d3] io
PCI: 00:05.2 20 <- [0x0000002cf0 - 0x0000002cff] io
PCI: 00:05.2 24 <- [0x00f2248000 - 0x00f2248fff] mem

pci_dev_set_resources(struct device *dev)
PCI: 00:06.0 1c <- [0x0000001000 - 0x0000001fff] bus 01 io
PCI: 00:06.0 20 <- [0x00f2100000 - 0x00f21fffff] bus 01 mem

pci_dev_set_resources(struct device *dev)
PCI: 01:00.0 10 <- [0x0000001880 - 0x000000188f] io
PCI: 01:00.0 14 <- [0x00f2110000 - 0x00f21107ff] mem
PCI: 01:00.0 30 <- [0x00f2111000 - 0x00f21117ff] romem

pci_dev_set_resources(struct device *dev)
PCI: 01:01.0 10 <- [0x0000001000 - 0x00000010ff] io
PCI: 01:01.0 30 <- [0x00f2100000 - 0x00f2107fff] romem

pci_dev_set_resources(struct device *dev)
PCI: 01:02.0 10 <- [0x0000001400 - 0x00000014ff] io
PCI: 01:02.0 30 <- [0x00f2108000 - 0x00f210ffff] romem

pci_dev_set_resources(struct device *dev)
PCI: 01:04.0 10 <- [0x00f2112000 - 0x00f21127ff] mem
PCI: 01:04.0 14 <- [0x0000001800 - 0x000000187f] io

pci_dev_set_resources(struct device *dev)
PCI: 00:06.1 10 <- [0x00f2240000 - 0x00f2243fff] mem

pci_dev_set_resources(struct device *dev)
PCI: 00:08.0 10 <- [0x00f2249000 - 0x00f2249fff] mem
PCI: 00:08.0 14 <- [0x0000003060 - 0x0000003067] io
PCI: 00:08.0 18 <- [0x00f224c000 - 0x00f224c0ff] mem
PCI: 00:08.0 1c <- [0x00f224e000 - 0x00f224e00f] mem

pci_dev_set_resources(struct device *dev)
PCI: 00:09.0 10 <- [0x00f224a000 - 0x00f224afff] mem
PCI: 00:09.0 14 <- [0x0000003070 - 0x0000003077] io
PCI: 00:09.0 18 <- [0x00f224d000 - 0x00f224d0ff] mem
PCI: 00:09.0 1c <- [0x00f224f000 - 0x00f224f00f] mem

pci_dev_set_resources(struct device *dev)
PCI: 00:0f.0 24 <- [0x00e0000000 - 0x00efffffff] bus 07 prefmem
PCI: 00:0f.0 20 <- [0x00f0000000 - 0x00f20fffff] bus 07 mem

pci_dev_set_resources(struct device *dev)
PCI: 07:00.0 10 <- [0x00f0000000 - 0x00f0ffffff] mem
PCI: 07:00.0 14 <- [0x00e0000000 - 0x00efffffff] prefmem64
PCI: 07:00.0 1c <- [0x00f1000000 - 0x00f1ffffff] mem64
PCI: 07:00.0 30 <- [0x00f2000000 - 0x00f201ffff] romem
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:18.0 cmd <- 140
0x55 status: 01
PCI: 00:00.0 subsystem <- 1462/9282
PCI: 00:00.0 cmd <- 146
0x55 status: 00
PCI: 00:01.0 subsystem <- 1462/9282
PCI: 00:01.0 cmd <- 14f
0x55 status: 5a
mcp55 lpc decode:PNP: 002e.0, base=0x000003f0, end=0x000003f7
mcp55 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff
mcp55 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
mcp55 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
w83627ehg hwm smbus enabled
mcp55 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000297
PCI: 00:01.1 subsystem <- 1462/9282
PCI: 00:01.1 cmd <- 141
0x55 status: 00
PCI: 00:01.2 cmd <- 540
0x55 status: 00
PCI: 00:01.3 cmd <- 142
0x55 status: 00
PCI: 00:02.0 subsystem <- 1462/9282
PCI: 00:02.0 cmd <- 142
0x55 status: 47
PCI: 00:02.1 subsystem <- 1462/9282
PCI: 00:02.1 cmd <- 142
0x55 status: 00
PCI: 00:04.0 subsystem <- 1462/9282
PCI: 00:04.0 cmd <- 141
0x55 status: 00
PCI: 00:05.0 subsystem <- 1462/9282
PCI: 00:05.0 cmd <- 143
0x55 status: 00
PCI: 00:05.1 subsystem <- 1462/9282
PCI: 00:05.1 cmd <- 143
0x55 status: 00
PCI: 00:05.2 subsystem <- 1462/9282
PCI: 00:05.2 cmd <- 143
0x55 status: 00
PCI: 00:06.0 bridge ctrl <- 0a03
PCI: 00:06.0 cmd <- 147
0x55 status: 00
PCI: 01:00.0 cmd <- 1c3
0x55 status: 00
PCI: 01:01.0 cmd <- 143
0x55 status: 00
PCI: 01:02.0 cmd <- 143
0x55 status: 00
PCI: 01:04.0 cmd <- 1c3
0x55 status: 00
PCI: 00:06.1 subsystem <- 1462/9282
PCI: 00:06.1 cmd <- 142
0x55 status: 00
PCI: 00:08.0 subsystem <- 1462/9282
PCI: 00:08.0 cmd <- 143
0x55 status: 00
PCI: 00:09.0 subsystem <- 1462/9282
PCI: 00:09.0 cmd <- 143
0x55 status: 00
PCI: 00:0a.0 bridge ctrl <- 0003
PCI: 00:0a.0 cmd <- 140
0x55 status: 00
PCI: 00:0b.0 bridge ctrl <- 0003
PCI: 00:0b.0 cmd <- 140
0x55 status: 00
PCI: 00:0c.0 bridge ctrl <- 0003
PCI: 00:0c.0 cmd <- 140
0x55 status: 00
PCI: 00:0d.0 bridge ctrl <- 0003
PCI: 00:0d.0 cmd <- 140
0x55 status: 00
PCI: 00:0e.0 bridge ctrl <- 0003
PCI: 00:0e.0 cmd <- 140
0x55 status: 00
PCI: 00:0f.0 bridge ctrl <- 000b
PCI: 00:0f.0 cmd <- 147
0x55 status: 00
PCI: 07:00.0 cmd <- 143
0x55 status: 00
PCI: 00:18.1 subsystem <- 1462/9282
PCI: 00:18.1 cmd <- 140
0x55 status: 00
PCI: 00:18.2 subsystem <- 1462/9282
PCI: 00:18.2 cmd <- 140
0x55 status: 00
PCI: 00:18.3 cmd <- 140
0x55 status: 00
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x00007000, offset=0x00110000, code_size=0x0000005b
Initializing CPU #0
CPU: vendor AMD device 40f32
CPU: family 0f, model 43, stepping 02
Enabling cache

Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
start_mtrr00000000
last_mtrr00000010
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
start_mtrr00000018
last_mtrr00000058
DONE fixed MTRRs
Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's

MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled

CPU model AMD Athlon(tm) 64 X2 Dual Core Processor 3800+
Setting up local apic... apic_id: 0x00 done.
ECC Disabled
CPU #0 Initialized
All AP CPUs stopped
PCI: 00:18.0 init
PCI: 00:01.0 init
set power off after power fail
RTC Init
RTC: Checksum invalid zeroing cmos
Invalid CMOS LB checksum
PNP: 002e.0 init
PNP: 002e.2 init
PNP: 002e.5 init
PNP: 002e.a init
PNP: 002e.b init
PCI: 00:01.1 init
PCI: 00:02.1 init
PCI: 00:04.0 init
IDE0
PCI: 00:05.0 init
SATA S \0x09SATA P
PCI: 00:05.1 init
SATA S \0x09SATA P
PCI: 00:05.2 init
SATA S \0x09SATA P
PCI: 00:06.0 init
dev_root mem base = 0x00e0000000
[0x50] <-- 0xe0000000
PCI: 00:06.1 init
base = f2240000
codec_mask = 01
codec viddid: 10ec0883
No verb!
PCI: 00:08.0 init
MCP55 MAC PHY ID 0x00070400 PHY ADDR 32
PCI: 00:09.0 init
MCP55 MAC PHY ID 0x00070400 PHY ADDR 1
PCI: 00:0a.0 init
PCI: 00:0b.0 init
PCI: 00:0c.0 init
PCI: 00:0d.0 init
PCI: 00:0e.0 init
PCI: 00:0f.0 init
PCI: 00:18.1 init
PCI: 00:18.2 init
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 00:01.2 init
PCI: 00:01.3 init
PCI: 01:00.0 init
rom address for PCI: 01:00.0 = f2111000
dump_mem:
f2111000: 55 aa 04 e9 fb 01 01 10 52 13 36 50 64 19 05 10
f2111010: 20 02 00 00 00 00 00 00 1e 00 36 00 00 00 50 43
f2111020: 49 52 95 17 03 00 00 00 18 00 00 ff 00 00 04 00
f2111030: 00 00 00 80 00 00 24 50 6e 50 01 02 00 00 00 dd
f2111040: 95 17 03 00 6e 00 8e 01 ff 00 00 40 01 02 00 00
f2111050: 00 00 00 00 00 00 0d 0a 41 63 63 65 73 73 20 73
f2111060: 79 73 74 65 6d 20 42 49 4f 53 20 56 00 2e 20 43
f2111070: 6f 70 79 72 69 67 68 74 20 28 43 29 20 4f 4b 42
f2111080: 20 53 41 50 52 20 31 39 39 33 2d 32 30 30 36 00
f2111090: 20 73 2f 6e 20 00 0d 0a 00 0d 0a 3f 41 43 43 4f
f21110a0: 52 44 20 42 49 4f 53 2d 00 46 41 54 41 4c 2d 00
f21110b0: 0d 0a 53 79 73 74 65 6d 20 68 61 6c 74 65 64 00
f21110c0: 52 65 73 65 74 20 68 61 72 64 77 61 72 65 2e 2e
f21110d0: 2e 00 0d 0a 4c 6f 61 64 69 6e 67 20 69 6d 61 67
f21110e0: 65 2e 2e 2e 00 47 65 74 74 69 6e 67 20 73 2f 6e
f21110f0: 2e 2e 2e 00 4f 4b 0d 0a 00 53 65 61 72 63 68 69
header signature aa55
Class Code mismatch ROM 000000ff, dev 00ff0000
copying non-VGA ROM Image from 0xf2111000 to 0xd0000, 0x800 bytes
dump_mem:
000d0000: 55 aa 04 e9 fb 01 01 10 52 13 36 50 64 19 05 10
000d0010: 20 02 00 00 00 00 00 00 1e 00 36 00 00 00 50 43
000d0020: 49 52 95 17 03 00 00 00 18 00 00 ff 00 00 04 00
000d0030: 00 00 00 80 00 00 24 50 6e 50 01 02 00 00 00 dd
000d0040: 95 17 03 00 6e 00 8e 01 ff 00 00 40 01 02 00 00
000d0050: 00 00 00 00 00 00 0d 0a 41 63 63 65 73 73 20 73
000d0060: 79 73 74 65 6d 20 42 49 4f 53 20 56 00 2e 20 43
000d0070: 6f 70 79 72 69 67 68 74 20 28 43 29 20 4f 4b 42
000d0080: 20 53 41 50 52 20 31 39 39 33 2d 32 30 30 36 00
000d0090: 20 73 2f 6e 20 00 0d 0a 00 0d 0a 3f 41 43 43 4f
000d00a0: 52 44 20 42 49 4f 53 2d 00 46 41 54 41 4c 2d 00
000d00b0: 0d 0a 53 79 73 74 65 6d 20 68 61 6c 74 65 64 00
000d00c0: 52 65 73 65 74 20 68 61 72 64 77 61 72 65 2e 2e
000d00d0: 2e 00 0d 0a 4c 6f 61 64 69 6e 67 20 69 6d 61 67
000d00e0: 65 2e 2e 2e 00 47 65 74 74 69 6e 67 20 73 2f 6e
000d00f0: 2e 2e 2e 00 4f 4b 0d 0a 00 53 65 61 72 63 68 69
dump_mem:
000d1000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d1010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d1020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d1030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d1040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d1050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d1060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d1070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d1080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d1090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d10a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d10b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d10c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d10d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d10e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d10f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
entering emulator
0000:7004: 22 ILLEGAL EXTENDED X86 OPCODE!
halt_sys: file 
/root/Linuxbios/LinuxBIOSv2/src/devices/emulator/x86emu/ops2.c, line 60
PCI: 01:01.0 init
rom address for PCI: 01:01.0 = f2100000
dump_mem:
f2100000: 55 aa 40 eb 6e 00 00 00 00 00 00 00 00 00 00 00
f2100010: 00 00 00 00 00 00 00 00 50 00 30 00 00 00 00 00
f2100020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f2100030: 24 50 6e 50 01 02 00 00 00 81 72 11 12 f0 6d 00
f2100040: 68 00 00 00 10 e0 00 00 00 00 00 00 00 00 00 00
f2100050: 50 43 49 52 72 11 12 f0 00 00 18 00 00 00 00 10
f2100060: 40 00 01 00 00 80 00 00 53 49 41 33 00 41 6e 63
f2100070: 75 64 00 1e 06 66 60 fc 0e 1f 0e 07 8b d8 be aa
f2100080: 01 e8 16 01 bf 10 00 b8 0a b1 cd 1a 0f 82 81 00
f2100090: 0a e4 75 7d 8b d1 81 e2 fc ff 74 75 80 c2 14 33
f21000a0: db b9 08 01 bf 00 02 8b f7 e8 9c 00 be a0 02 80
f21000b0: 3c 00 74 5d 80 3c ff 74 58 e8 de 00 bf 00 02 8b
f21000c0: f7 80 c2 0c b0 01 66 c1 e0 1d 66 ef 80 c2 08 b9
f21000d0: 06 00 f3 6e 80 c2 f8 66 33 c0 66 ef 80 c2 f4 8b
f21000e0: 1e 48 02 8b 0e 4c 02 e3 0d bf 00 02 e8 59 00 8a
f21000f0: 0e 02 00 e8 0a 01 88 0e 02 00 c1 e1 ff ff ff ff
header signature aa55
Class Code mismatch ROM 00100000, dev 00020000
copying non-VGA ROM Image from 0xf2100000 to 0xd0800, 0x8000 bytes
dump_mem:
000d0000: 55 aa 04 e9 fb 01 01 10 52 13 36 50 64 19 05 10
000d0010: 20 02 00 00 00 00 00 00 1e 00 36 00 00 00 50 43
000d0020: 49 52 95 17 03 00 00 00 18 00 00 ff 00 00 04 00
000d0030: 00 00 00 80 00 00 24 50 6e 50 01 02 00 00 00 dd
000d0040: 95 17 03 00 6e 00 8e 01 ff 00 00 40 01 02 00 00
000d0050: 00 00 00 00 00 00 0d 0a 41 63 63 65 73 73 20 73
000d0060: 79 73 74 65 6d 20 42 49 4f 53 20 56 00 2e 20 43
000d0070: 6f 70 79 72 69 67 68 74 20 28 43 29 20 4f 4b 42
000d0080: 20 53 41 50 52 20 31 39 39 33 2d 32 30 30 36 00
000d0090: 20 73 2f 6e 20 00 0d 0a 00 0d 0a 3f 41 43 43 4f
000d00a0: 52 44 20 42 49 4f 53 2d 00 46 41 54 41 4c 2d 00
000d00b0: 0d 0a 53 79 73 74 65 6d 20 68 61 6c 74 65 64 00
000d00c0: 52 65 73 65 74 20 68 61 72 64 77 61 72 65 2e 2e
000d00d0: 2e 00 0d 0a 4c 6f 61 64 69 6e 67 20 69 6d 61 67
000d00e0: 65 2e 2e 2e 00 47 65 74 74 69 6e 67 20 73 2f 6e
000d00f0: 2e 2e 2e 00 4f 4b 0d 0a 00 53 65 61 72 63 68 69
dump_mem:
000d1000: 55 aa 40 eb 6e 00 00 00 00 00 00 00 00 00 00 00
000d1010: 00 00 00 00 00 00 00 00 50 00 30 00 00 00 00 00
000d1020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d1030: 24 50 6e 50 01 02 00 00 00 81 72 11 12 f0 6d 00
000d1040: 68 00 00 00 10 e0 00 00 00 00 00 00 00 00 00 00
000d1050: 50 43 49 52 72 11 12 f0 00 00 18 00 00 00 00 10
000d1060: 40 00 01 00 00 80 00 00 53 49 41 33 00 41 6e 63
000d1070: 75 64 00 1e 06 66 60 fc 0e 1f 0e 07 8b d8 be aa
000d1080: 01 e8 16 01 bf 10 00 b8 0a b1 cd 1a 0f 82 81 00
000d1090: 0a e4 75 7d 8b d1 81 e2 fc ff 74 75 80 c2 14 33
000d10a0: db b9 08 01 bf 00 02 8b f7 e8 9c 00 be a0 02 80
000d10b0: 3c 00 74 5d 80 3c ff 74 58 e8 de 00 ff 00 ff ff
000d10c0: f7 80 c2 0c b0 01 66 c1 e0 1d 66 ef 80 c2 08 b9
000d10d0: 06 00 f3 6e 80 c2 f8 66 33 c0 66 ef ff ff ff ff
000d10e0: 1e 48 02 8b 0e 4c 02 e3 0d bf 00 02 ff ff ff ff
000d10f0: 0e 02 00 e8 ff ff ff ff ff ff ff ff ff ff ff ff
entering emulator
0000:7004: 22 ILLEGAL EXTENDED X86 OPCODE!
halt_sys: file 
/root/Linuxbios/LinuxBIOSv2/src/devices/emulator/x86emu/ops2.c, line 60
PCI: 01:02.0 init
rom address for PCI: 01:02.0 = f2108000
dump_mem:
f2108000: 55 aa 40 eb 6e 00 00 00 00 00 00 00 00 00 00 00
f2108010: 00 00 00 00 00 00 00 00 50 00 30 00 00 00 00 00
f2108020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f2108030: 24 50 6e 50 01 02 00 00 00 81 72 11 12 f0 6d 00
f2108040: 68 00 00 00 10 e0 00 00 00 00 00 00 00 00 00 00
f2108050: 50 43 49 52 72 11 12 f0 00 00 18 00 00 00 00 10
f2108060: 40 00 01 00 00 80 00 00 53 49 41 33 00 41 6e 63
f2108070: 75 64 00 1e 06 66 60 fc 0e 1f 0e 07 8b d8 be aa
f2108080: 01 e8 16 01 bf 10 00 b8 0a b1 cd 1a 0f 82 81 00
f2108090: 0a e4 75 7d 8b d1 81 e2 fc ff 74 75 80 c2 14 33
f21080a0: db b9 08 01 bf 00 02 8b f7 e8 9c 00 be a0 02 80
f21080b0: 3c 00 74 5d 80 3c ff 74 58 e8 de 00 bf 00 02 8b
f21080c0: f7 80 c2 0c b0 01 66 c1 e0 1d 66 ef 80 c2 08 b9
f21080d0: 06 00 f3 6e 80 c2 f8 66 33 c0 66 ef 80 c2 f4 8b
f21080e0: 1e 48 02 8b 0e 4c 02 e3 0d bf 00 02 e8 59 00 8a
f21080f0: 0e 02 00 e8 0a 01 88 0e 02 00 c1 e1 09 74 0c 33
header signature aa55
Class Code mismatch ROM 00100000, dev 00020000
copying non-VGA ROM Image from 0xf2108000 to 0xd8800, 0x8000 bytes
dump_mem:
000d0000: 08 09 0a e9 fb 01 01 10 52 13 36 50 64 19 05 10
000d0010: 20 02 00 00 00 00 00 00 1e 00 36 00 00 00 50 43
000d0020: 49 52 95 17 03 00 00 00 18 00 00 ff 00 00 04 00
000d0030: 00 00 00 80 00 00 24 50 6e 50 01 02 00 00 00 dd
000d0040: 95 17 03 00 6e 00 8e 01 ff 00 00 40 01 02 00 00
000d0050: 00 00 00 00 00 00 0d 0a 41 63 63 65 73 73 20 73
000d0060: 79 73 74 65 6d 20 42 49 4f 53 20 56 00 2e 20 43
000d0070: 6f 70 79 72 69 67 68 74 20 28 43 29 20 4f 4b 42
000d0080: 20 53 41 50 52 20 31 39 39 33 2d 32 30 30 36 00
000d0090: 20 73 2f 6e 20 00 0d 0a 00 0d 0a 3f 41 43 43 4f
000d00a0: 52 44 20 42 49 4f 53 2d 00 46 41 54 41 4c 2d 00
000d00b0: 0d 0a 53 79 73 74 65 6d 20 68 61 6c 74 65 64 00
000d00c0: 52 65 73 65 74 20 68 61 72 64 77 61 72 65 2e 2e
000d00d0: 2e 00 0d 0a 4c 6f 61 64 69 6e 67 20 69 6d 61 67
000d00e0: 65 2e 2e 2e 00 47 65 74 74 69 6e 67 20 73 2f 6e
000d00f0: 2e 2e 2e 00 4f 4b 0d 0a 00 53 65 61 72 63 68 69
dump_mem:
000d1000: 55 aa 40 eb 6e 00 c7 87 00 00 00 00 00 00 00 00
000d1010: 00 00 00 00 00 00 00 00 50 00 30 00 00 00 00 00
000d1020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000d1030: 24 50 6e 50 01 02 00 00 00 81 72 11 12 f0 6d 00
000d1040: 68 00 00 00 10 e0 00 00 00 00 00 00 00 00 00 00
000d1050: 50 43 49 52 72 11 12 f0 00 00 18 00 00 00 00 10
000d1060: 40 00 01 00 00 80 00 00 53 49 41 33 00 41 6e 63
000d1070: 75 64 00 1e 06 66 60 fc 0e 1f 0e 07 8b d8 be aa
000d1080: 01 e8 16 01 bf 10 00 b8 0a b1 cd 1a 0f 82 81 00
000d1090: 0a e4 75 7d 8b d1 81 e2 fc ff 74 75 80 c2 14 33
000d10a0: db b9 08 01 bf 00 02 8b f7 e8 9c 00 be a0 02 80
000d10b0: 3c 00 74 5d 80 3c ff 74 58 e8 de 00 ff 00 ff ff
000d10c0: f7 80 c2 0c b0 01 66 c1 e0 1d 66 ef 80 c2 08 b9
000d10d0: 06 00 f3 6e 80 c2 f8 66 33 c0 66 ef ff ff ff ff
000d10e0: 1e 48 02 8b 0e 4c 02 e3 0d bf 00 02 ff ff ff ff
000d10f0: 0e 02 00 e8 ff ff ff ff ff ff ff ff ff ff ff ff
entering emulator
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
un-inited int vector
halt_sys: file 
/root/Linuxbios/LinuxBIOSv2/src/devices/emulator/x86emu/ops.c, line 4387
PCI: 01:04.0 init
PCI: 07:00.0 init
rom address for PCI: 07:00.0 = f2000000
dump_mem:
f2000000: 55 aa 7e eb 4b 37 34 30 30 e9 4c 19 77 cc 56 49
f2000010: 44 45 4f 20 0d 00 00 00 08 01 79 11 00 00 49 42
f2000020: 4d 20 56 47 41 20 43 6f 6d 70 61 74 69 62 6c 65
f2000030: 01 00 00 00 80 10 86 99 31 30 2f 32 34 2f 30 36
f2000040: 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00
f2000050: e9 77 dd 00 43 10 1d 82 ff cf ef 7f 00 10 00 80
f2000060: ff ff ff 7f 00 00 00 80 22 00 a5 71 e9 4d b8 e9
f2000070: 54 b8 50 4d 49 44 6c 00 6f 00 00 00 00 a0 00 b0
f2000080: 00 b8 00 c0 00 33 7e ca 9b 00 02 00 04 00 6a 21
f2000090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f20000a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f20000b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f20000c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f20000d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f20000e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f20000f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
header signature aa55
copying VGA ROM Image from 0xf2000000 to 0xc0000, 0xfc00 bytes
dump_mem:
000c0000: 55 aa 7e eb 4b 37 34 30 30 e9 4c 19 77 cc 56 49
000c0010: 44 45 4f 20 0d 00 00 00 08 01 79 11 00 00 49 42
000c0020: 4d 20 56 47 41 20 43 6f 6d 70 61 74 69 62 6c 65
000c0030: 01 00 00 00 80 10 86 99 31 30 2f 32 34 2f 30 36
000c0040: 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00
000c0050: e9 77 dd 00 43 10 1d 82 ff cf ef 7f 00 10 00 80
000c0060: ff ff ff 7f 00 00 00 80 22 00 a5 71 e9 4d b8 e9
000c0070: 54 b8 50 4d 49 44 6c 00 6f 00 00 00 00 a0 00 b0
000c0080: 00 b8 00 c0 00 33 7e ca 9b 00 02 00 04 00 6a 21
000c0090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
000c00a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
000c00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
000c00c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
000c00d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
000c00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
000c00f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
000c0100: ff ff ff ff 48 57 45 41 50 43 49 52 de 10 d1 01
000c0110: 00 00 18 00 00 00 00 03 7e 00 01 00 00 80 00 00
000c0120: 41 53 55 53 20 45 4e 37 33 30 30 54 43 35 31 32
000c0130: 20 56 47 41 20 42 49 4f 53 20 56 65 72 73 69 6f
000c0140: 6e 20 35 2e 37 32 2e 32 32 2e 34 33 2e 41 53 32
000c0150: 39 0d 0a 00 44 4a 48 01 c2 01 90 01 14 28 14 28
000c0160: 45 4e 37 33 30 30 54 43 35 31 32 00 00 00 00 00
000c0170: 00 56 65 72 73 69 6f 6e 20 20 35 2e 37 32 2e 32
000c0180: 32 2e 34 33 2e 30 30 20 0d 0a 00 43 6f 70 79 72
000c0190: 69 67 68 74 20 28 43 29 20 31 39 39 36 2d 32 30
000c01a0: 30 36 20 4e 56 49 44 49 41 20 43 6f 72 70 2e 0d
000c01b0: 0a 00 00 00 ba 91 98 96 91 9a 9a 8d 96 91 98 df
000c01c0: ad 9a 93 9a 9e 8c 9a df d2 df b1 90 8b df b9 90
000c01d0: 8d df af 8d 90 9b 8a 9c 8b 96 90 91 df aa 8c 9a
000c01e0: f2 f5 ff ff ff 47 37 32 20 42 6f 61 72 64 20 2d
000c01f0: 20 70 33 38 31 6e 30 20 20 00 00 00 00 00 00 00
000c0200: 00 00 00 00 00 00 00 00 43 68 69 70 20 52 65 76
000c0210: 20 20 20 00 00 00 00 00 00 00 00 00 ff b8 42 49
000c0220: 54 00 00 01 0c 06 11 46 32 01 04 00 8e 02 42 02
000c0230: 19 00 92 02 43 01 0e 00 ab 02 44 01 04 00 b9 02
000c0240: 49 01 0e 00 bd 02 4c 01 02 00 cb 02 74 01 12 00
000c0250: cd 02 4d 01 0d 00 df 02 4e 00 00 00 00 00 50 01
000c0260: 19 00 ec 02 53 02 15 00 05 03 54 01 02 00 1a 03
000c0270: 55 01 03 00 1c 03 56 01 06 00 1f 03 63 00 00 00
000c0280: 00 00 69 02 25 00 25 03 73 01 10 00 4a 03 00 00
000c0290: 00 00 43 22 72 05 00 00 00 00 00 00 a8 07 00 00
000c02a0: 00 00 00 00 00 00 02 04 55 55 00 00 00 00 00 00
000c02b0: 00 00 00 96 5d ba 30 31 5f a8 96 de 96 10 60 22
000c02c0: 60 2a 60 4a 60 7a 60 7a 60 22 60 04 d1 3a cf 40
000c02d0: cf 46 cf 5e cf 76 cf 8e cf a6 cf be cf d6 cf cb
000c02e0: 60 08 ff 5f 00 00 00 00 00 00 00 00 64 df 00 00
000c02f0: 66 e0 00 00 00 00 00 00 29 df 00 00 c6 e0 00 00
entering emulator
halt_sys: file 
/root/Linuxbios/LinuxBIOSv2/src/devices/emulator/x86emu/ops.c, line 4387
Devices initialized
Writing IRQ routing tables to 0xf0000...done.
Assigning IRQ 3 to 0:6.1
Readback = 3
Assigning IRQ 11 to 0:1.1
Readback = 11
Assigning IRQ 11 to 0:1.3
Readback = 11
Assigning IRQ 10 to 0:8.0
Readback = 10
Assigning IRQ 10 to 0:9.0
Readback = 10
Assigning IRQ 7 to 0:5.0
Readback = 7
Assigning IRQ 10 to 0:5.1
Readback = 10
Assigning IRQ 11 to 0:5.2
Readback = 11
Assigning IRQ 10 to 7:0.0
Readback = 10
Assigning IRQ 11 to 1:0.0
Readback = 11
Assigning IRQ 11 to 1:1.0
Readback = 11
Assigning IRQ 7 to 1:2.0
Readback = 7
smp_write_processor
cpu->path.u.apic.apic_id
00apic_version
10cpu_flag
03cpu_features
00040f32cpu_feature_flags
178bfbffDevice found
PCI: 0011c2a0f2244000
bus_isa 00000008
bus_mcp55[0] 00000000
bus_mcp55[1] 00000001
apicid_mcp55 00000001
Wrote the mp table end at: 00000020 - 00000270
Moving GDT to 0x500...ok
Adjust low_table_end from 0x00000530 to 0x00001000
Adjust rom_table_end from 0x000f0400 to 0x00100000
Wrote linuxbios table at: 00000530 - 00000db4 checksum fc15

Welcome to elfboot, the open sourced starter.
January 2002, Eric Biederman.
Version 1.3

rom_stream: 0xfff80000 - 0xfff9ffff
Found ELF candidate at offset 0
header_offset is 0
Try to load at offset 0x0
New segment addr 0x100000 size 0x23ea0 offset 0xc0 filesize 0x9e28
(cleaned up) New segment addr 0x100000 size 0x23ea0 offset 0xc0 filesize 
0x9e28
New segment addr 0x1s23ea0 size 0x48egment addr 0x123ea0 size 0x48 
offset 0x9f00 filesize 0x48
Dropping non PT_LOAD segment
Dropping non PT_LOAD segment
Loading Segment: addr: 0x000000003ff7c000 memsz: 0x0000000000023ea0 
filesz: 0x0000000000009e28
Clearing Segment: addr: 0x000000003ff85e28 memsz: 0x000000000001a078
Loading Segment: addr: 0x000000003ff9fea0 memsz: 0x0000000000000048 
filesz: 0x0000000000000048
Jumping to boot code at 0x107b1c
.....

Here starts filo, and boots linux
I will send a patch a bit later.

I boot 2.4.21 kernel it works fine under stock BIOS is there any chance 
to make this kernel work under LinuxBIOS?

Best Regards,

George.

[George V. Adamov]

finally there is a patch which makes src/mainboard/msi/ms7250 from 
src/mainboard/msi/ms9285 (I used the most current version 3241 for ms9285).

I hope we will make ms7250 workable completely and place it to the 
coreboot tree ))))

George V. Adamov wrote:
> yhlu wrote:
> > On Thu, Apr 10, 2008 at 6:40 AM, Carl-Daniel Hailfinger
> >  wrote:
> > > Hi,
> > >
> > > On 10.04.2008 14:16, George V. Adamov wrote:
> > > > Hi evrybody!
> > > > I have already asked once about this problem, but no responce resieved,
> > > > so the question is - are the motherboards ms-7260 amd Gigabyte based on
> > > > MCP 55 truly full functional? I mean devices pluged in their pci slots -
> > > > are they really  operatable?
> > >
> > > This depends a lot on the boards. Unfortunately, there is not public
> > > documentation about MCP55 internals.
> > > > /*here is the old message, perhaps somebody could give an idea what the
> > > > trouble with pci slots could be*/
> > > >
> > > > MSI MS7250 - MCP 55 based motherboard.
> > > > I have troubles with interrupts of devices plug in PCI slots.
> > > >
> > > > If  I use irq_tables.c with only record for irq router (just like it is
> > > > for Gigabyte based on MCP55 and MSI7260 ):
> > > >
> > > > write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8,
> > > > 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
> > > >
> > > > Linux says that no interrupt for pin A assigned for devices in pcis slots.
> > > >
> > > > I grubbed IRQ table with getpir and added records for other devices.
> > > > As for pci slots it looks like
> > > >
> > > > /*slot0*/
> > > > write_pirq_info(pirq_info, 0x01, ((sbdn+0x00)<<3)|0, 0x80/*80*/, 0x0800,
> > > > 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x1, 0x0);
> > > >  pirq_info++; slot_num++;
> > > >
> > > > /*slot1*/
> > > >  write_pirq_info(pirq_info, 0x01, ((sbdn+0x01)<<3)|0,
> > > > 0x81/*81*/,/*0x0800*/ 0x0800, 0x00,/*0x0*/ 0x0000, 0x00,/*0x0*/ 0x0000,
> > > > 0x00, 0x00000, 0x2, 0x0);
> > > >  pirq_info++; slot_num++;
> > > >
> > > > /*slot2*/
> > > >  write_pirq_info(pirq_info, 0x01, ((sbdn+0x02)<<3)|0, 0x82,/*0x4ca0*/
> > > > 0x4c80, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x3, 0x0);
> > > >
> > > > And I also used function pci_assign_irqs - to write irqs from the table
> > > > into configuration space of each device
> > > >
> > > > After this the device plug  in  pci slot0 starts up (it was a network
> > > > card), but running cat /proc/interrupts - showed strange CPU time for
> > > > eth0 (at least 3 orders higher than any other device) it was also easy
> > > > to note that system was a bit slow with ethernet card pluged. But at
> > > > least card worked ;)
> > > >
> > > > I tried to plug it to slot1 and slot2 - when Linux tried to load module
> > > > for the card I got NMI ((((
> > > >
> > > > Any ideas what the trouble is ?
> > >
> > > Can you post a full boot log with debugging enabled? Please post a patch
> > > against current svn HEAD as well. That way, we have a chance to help you.
> >
> > please make sure you are using 64bit SMP kernel.
> >
> > BTW. the irq_tables.c is only used for discovering of peer root bus
> > other than bus0 when acpi is not there.
> >
> > YH
> >
> > YH
>
> Here is the debug I recieve via com port:
> There are also some additional messages I needed porting code on 
> MS7250, in comments I wrote about a little bug which seemed to me not 
> so serious.
>
> LinuxBIOS-2.0.0_Fallback Thu Mar 20 16:51:56 UTC 2008 starting...
> bist==0 cpus inited
> *sysinfo range: [000cf000,000cf730)
> bsp_apicid=00
> core0 started:
> setup_coherent_ht_domain()started ap apicid:  01
> start_other_cores()SBLink=00
> NC node|link=00
> begin msr fid, vid 310c12120c0c0202
> end   msr fid, vid 310c120c0c0c020c
> mcp55_num:01
> ht reset -
>
> LinuxBIOS-2.0.0_Fallback Thu Mar 20 16:51:56 UTC 2008 starting...
> bist==0 cpus inited
> *sysinfo range: [000cf000,000cf730)
> bsp_apicid=00
> core0 started:
> setup_coherent_ht_domain()started ap apicid:  01
> start_other_cores()SBLink=00
> NC node|link=00
> begin msr fid, vid 310c120c0c0c020c
> end   msr fid, vid 310c120c0c0c020c
> mcp55_num:01
> allow_all_aps_stopfill_mem_ctrlenable_smbus()memreset_setup()sdram_initialize
> started
>
> Ram1.00
> setting up CPU00Ram2.00
> sdram_set_spd_registers: starting
> activate_spd_rom: nothing needs to be done
> DDR2 DIMM FOUND CH0
> DDR2 DIMM FOUND CH1
> spd_enable_2channels
> Enabling dual channel memory
> Unbuffered
> 333Mhz
> RAM: 0x00100000 KB
> Ram3
> \0x09dimm_mask = 00000011
> \0x09x4_mask = 00000000
> \0x09x16_mask = 00000000
> \0x09single_rank_mask = 00000001
> \0x09ODC = 00111222
> \0x09Addr Timing= 00202220
> clock started
> Initializing memory:  done
> Setting variable MTRR 02, base: 0000MB, range: 0400MB, type WB
> DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=1a done
> DQS Training:DQSPos: 00 done
> DQS Training:RcvrEn:Pass2: 00 CTLRMaxDelay=34 done
> DQS Training:tsc[00]=000000003f141d3a
> DQS Training:tsc[01]=0000000040d045c6
> DQS Training:tsc[02]=0000000040d045cf
> DQS Training:tsc[03]=000000007aea695f
> DQS Training:tsc[04]=000000007c990099
> Ram4
> sdram_initialize - finished
> sdram_initialize
>  dump_mem: /*I dont know why, but part of a flash rom seemed to be 
> shadowed, Fallback image should be located here*/
> fffe0000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> fffe0010: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> fffe0020: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> fffe0030: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> fffe0040: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> fffe0050: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> fffe0060: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> fffe0070: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> fffe0080: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> fffe0090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> fffe00a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> fffe00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> fffe00c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> fffe00d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> fffe00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> fffe00f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> dump_mem: /*mem after initialization*/
> 00100000: 78 56 34 12 21 43 65 87 89 67 45 23 32 54 76 98
> 00100010: 24 58 38 59 24 67 49 30 95 07 49 24 33 87 93 99
> 00100020: 42 56 38 40 45 52 46 38 63 21 43 29 94 78 06 05
> 00100030: 45 90 34 12 67 34 72 98 34 76 38 12 23 76 58 34
> 00100040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00100050: ff ff ff ff ff ff ff ff 00 00 00 6f 00 00 00 00
> 00100060: 00 00 00 00 00 00 00 00 6f 2b 00 00 00 64 ff ff
> 00100070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00100080: fe fe fe fe fe fe fe fe fe fe fe fe fe fe fe fe
> 00100090: 01 01 01 01 01 01 01 01 85 fe 01 01 01 f4 b4 c1
> 001000a0: fe fe fe fe fe fe fe fe 00 00 10 7a 10 00 00 00
> 001000b0: 01 01 01 01 01 01 01 01 c5 fe 01 01 00 f4 94 c1
> 001000c0: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
> 001000d0: fe fe fe fe fe fe fe fe 00 00 00 6e 00 00 00 00
> 001000e0: fe fe fe fe fe fe fe fe fe fe fe fe fe fe fe fe
> 001000f0: 01 01 01 01 01 01 01 01 c5 fe 01 01 00 fc fc d9
> 12345678v_esp=000cedec
> testx = 5a5a5a5a /*a small test write 0x5a5a5a5a to ram and read it 
> back to make sure it really works*/
> Copying data from cache to RAM -- switching to use RAM as stack... G 
> versionDone
> testx = 5a5a5a5a
> Disabling cache as ram now
> Clearing initial memory region: Done
> Copying LinuxBIOS to RAM. -AMD
> src=fffa0000 /*here I point directly on unshadowed part of flash chip 
> we will copy and use Normal Image*/
> dst=00100000
> dump_mem: /*dump to make sure I really copy what I need*/
> fffa0000: 00 47 02 00 df fe da ff fa 2e 0f 01 15 38 01 10
> fffa0010: 00 ea 02 01 b8 18 00 00 8e d8 8e c0 ff f6 ff ff
> fffa0020: 8e d0 8e e0 8e e8 b0 13 e6 80 fc 8d 3d 00 60 13
> fffa0030: 00 b9 00 a0 04 29 f9 c1 e9 02 31 c0 c1 3e 97 dd
> fffa0040: f3 ab 13 47 12 84 45 74 07 15 ef df ee be bc 23
> fffa0050: 6a 01 55 89 e5 21 30 a2 11 00 8d 1d a1 55 ff 7f
> fffa0060: fb bb 00 04 66 89 d8 89 da 66 ba 5d 89 47 00 89
> fffa0070: 57 04 83 c3 06 83 c7 08 81 ff bf ed 6e bb d0 25
> fffa0080: 75 e3 85 1d 28 08 b0 fe 6f 89 ec e8 fa 42 dc fd
> fffa0090: de 6e 30 b0 ee 0a f4 eb f9 4d eb 72 05 01 eb 6c
> fffa00a0: dc dc dc dc 02 eb 66 03 eb 60 04 eb 5a 05 eb 54
> fffa00b0: 7f f7 df dc 06 eb 4e 07 eb 48 6a 08 eb 44 90 90
> fffa00c0: 0b 09 eb 3c 6a 0a eb 38 37 37 77 37 0b eb 32 05
> fffa00d0: 0c eb 2c 0d eb 26 0e eb 20 8f fd dd 63 23 0f eb
> fffa00e0: 18 05 10 eb 12 6a 11 eb 0e 11 12 eb 06 6f ff ff
> fffa00f0: 77 05 13 eb 00 57 56 55 8d 6c 24 20 55 53 52 51
> dump_mem: /*and to make shure memory is zeroed*/
> 00100000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00100010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00100020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00100030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00100040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00100050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00100060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00100070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00100080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 00100090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 001000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 001000b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 001000c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 001000d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 001000e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 001000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> linxbios_ram.nrv2b length = 0000dd36
> linxbios_ram.bin   length = 00024700
> Jumping to LinuxBIOS.
> LinuxBIOS-2.0.0_Normal Thu Mar 20 16:51:40 UTC 2008 booting...
> Enumerating buses...
> APIC_CLUSTER: 0 enabled
> PCI_DOMAIN: 0000 enabled
>   PCI: 00:18.3 siblings=1
> CPU: APIC: 00 enabled
> PCI: pci_scan_bus for bus 00
> PCI: 00:18.0 [1022/1100] enabled
> PCI: 00:18.1 [1022/1101] enabled
> PCI: 00:18.2 [1022/1102] enabled
> PCI: 00:18.3 [1022/1103] enabled
> PCI: 00:00.0 [10de/0369] enabled
> PCI: 00:00.0 [10de/0369] enabled next_unitid: 0010
> PCI: pci_scan_bus for bus 00
> PCI: 00:00.0 [10de/0369] enabled
> PCI: 00:01.0 [10de/0360] enabled
> PCI: 00:01.1 [10de/0368] enabled
> PCI: 00:01.2 [10de/036a] enabled
> PCI: 00:01.3 [10de/036b] enabled
> PCI: 00:02.0 [10de/036c] enabled
> PCI: 00:02.1 [10de/036d] enabled
> PCI: 00:04.0 [10de/036e] enabled
> PCI: 00:05.0 [10de/037f] enabled
> PCI: 00:05.1 [10de/037f] enabled
> PCI: 00:05.2 [10de/037f] enabled
> PCI: 00:06.0 [10de/0370] enabled
> PCI: 00:06.1 [10de/0371] enabled
> PCI: 00:08.0 [10de/0373] enabled
> PCI: 00:09.0 [10de/0373] enabled
> PCI: 00:0a.0 [10de/0376] enabled
> PCI: 00:0b.0 [10de/0374] enabled
> PCI: 00:0c.0 [10de/0374] enabled
> PCI: 00:0d.0 [10de/0378] enabled
> PCI: 00:0e.0 [10de/0375] enabled
> PCI: 00:0f.0 [10de/0377] enabled
> PNP: 002e.0 enabled
> PNP: 002e.1 disabled
> PNP: 002e.2 enabled
> PNP: 002e.3 disabled
> PNP: 002e.5 enabled
> PNP: 002e.6 disabled
> PNP: 002e.7 disabled
> PNP: 002e.8 disabled
> PNP: 002e.9 disabled
> PNP: 002e.a enabled
> PNP: 002e.b enabled
> smbus: PCI: 00:01.1[0]->I2C: 01:50 enabled
> smbus: PCI: 00:01.1[0]->I2C: 01:51 enabled
> smbus: PCI: 00:01.1[0]->I2C: 01:52 enabled
> smbus: PCI: 00:01.1[0]->I2C: 01:53 enabled
> smbus: PCI: 00:01.1[0]->I2C: 01:54 enabled
> smbus: PCI: 00:01.1[0]->I2C: 01:55 enabled
> smbus: PCI: 00:01.1[0]->I2C: 01:56 enabled
> smbus: PCI: 00:01.1[0]->I2C: 01:57 enabled
> smbus: PCI: 00:01.1[1]->I2C: 02:51 enabled
> PCI: pci_scan_bus for bus 01
> PCI: 01:00.0 [1795/0003] enabled
> PCI: 01:01.0 [1172/f012] enabled
> PCI: 01:02.0 [1172/f012] enabled
> PCI: 01:04.0 [1106/3044] enabled
> PCI: pci_scan_bus returning with max=001
> PCI: pci_scan_bus for bus 02
> Disabling static device: PCI: 02:00.0
> PCI: pci_scan_bus returning with max=002
> PCI: pci_scan_bus for bus 03
> PCI: pci_scan_bus returning with max=003
> PCI: pci_scan_bus for bus 04
> PCI: pci_scan_bus returning with max=004
> PCI: pci_scan_bus for bus 05
> Disabling static device: PCI: 05:00.0
> PCI: pci_scan_bus returning with max=005
> PCI: pci_scan_bus for bus 06
> PCI: pci_scan_bus returning with max=006
> PCI: pci_scan_bus for bus 07
> PCI: 07:00.0 [10de/01d1] enabled
> PCI: pci_scan_bus returning with max=007
> PCI: pci_scan_bus returning with max=007
> PCI: pci_scan_bus returning with max=007
> done
> Allocating resources...
> Reading resources...
> PCI: 00:06.0 24 <- [0x00fff00000 - 0x00ffefffff] bus 01 prefmem
> PCI: 00:0a.0 1c <- [0x00fffff000 - 0x00ffffefff] bus 02 io
> PCI: 00:0a.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] bus 02 
> prefmem
> PCI: 00:0a.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 02 mem
> PCI: 00:0b.0 1c <- [0x00fffff000 - 0x00ffffefff] bus 03 io
> PCI: 00:0b.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] bus 03 
> prefmem
> PCI: 00:0b.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 03 mem
> PCI: 00:0c.0 1c <- [0x00fffff000 - 0x00ffffefff] bus 04 io
> PCI: 00:0c.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] bus 04 
> prefmem
> PCI: 00:0c.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 04 mem
> PCI: 00:0d.0 1c <- [0x00fffff000 - 0x00ffffefff] bus 05 io
> PCI: 00:0d.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] bus 05 
> prefmem
> PCI: 00:0d.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 05 mem
> PCI: 00:0e.0 1c <- [0x00fffff000 - 0x00ffffefff] bus 06 io
> PCI: 00:0e.0 24 <- [0xfffffffffff00000 - 0xffffffffffefffff] bus 06 
> prefmem
> PCI: 00:0e.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 06 mem
> PCI: 00:0f.0 1c <- [0x00fffff000 - 0x00ffffefff] bus 07 io
> Done reading resources.
> Allocating VGA resource PCI: 07:00.0
> Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:0f.0
> Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
> Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
> Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
> Setting resources...
> VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
> PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000003fff] io <node 0 link 0>
> PCI: 00:18.0 1b8 <- [0x00e0000000 - 0x00efffffff] prefmem <node 0 link 0>
> PCI: 00:18.0 1b0 <- [0x00f0000000 - 0x00f22fffff] mem <node 0 link 0>
>
> pci_dev_set_resources(struct device *dev)
> PCI: 00:01.0 14 <- [0x00f2244000 - 0x00f2244fff] mem
> PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] io
> PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] irq
> PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] drq
> PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] io
> PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] irq
> PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] io
> PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] io
> PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] irq
> PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] irq
> PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] io
> PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] irq
>
> pci_dev_set_resources(struct device *dev)
> PCI: 00:01.1 10 <- [0x0000002c00 - 0x0000002c3f] io
> PCI: 00:01.1 20 <- [0x0000002c40 - 0x0000002c7f] io
> PCI: 00:01.1 24 <- [0x0000002c80 - 0x0000002cbf] io
> PCI: 00:01.1 60 <- [0x0000002000 - 0x00000020ff] io
> PCI: 00:01.1 64 <- [0x0000002400 - 0x00000024ff] io
> PCI: 00:01.1 68 <- [0x0000002800 - 0x00000028ff] io
>
> pci_dev_set_resources(struct device *dev)
> PCI: 00:01.3 10 <- [0x00f2200000 - 0x00f223ffff] mem
>
> pci_dev_set_resources(struct device *dev)
> PCI: 00:02.0 10 <- [0x00f2245000 - 0x00f2245fff] mem
>
> pci_dev_set_resources(struct device *dev)
> PCI: 00:02.1 10 <- [0x00f224b000 - 0x00f224b0ff] mem
>
> pci_dev_set_resources(struct device *dev)
> PCI: 00:04.0 20 <- [0x0000002cc0 - 0x0000002ccf] io
>
> pci_dev_set_resources(struct device *dev)
> PCI: 00:05.0 10 <- [0x0000003000 - 0x0000003007] io
> PCI: 00:05.0 14 <- [0x0000003080 - 0x0000003083] io
> PCI: 00:05.0 18 <- [0x0000003010 - 0x0000003017] io
> PCI: 00:05.0 1c <- [0x0000003090 - 0x0000003093] io
> PCI: 00:05.0 20 <- [0x0000002cd0 - 0x0000002cdf] io
> PCI: 00:05.0 24 <- [0x00f2246000 - 0x00f2246fff] mem
>
> pci_dev_set_resources(struct device *dev)
> PCI: 00:05.1 10 <- [0x0000003020 - 0x0000003027] io
> PCI: 00:05.1 14 <- [0x00000030a0 - 0x00000030a3] io
> PCI: 00:05.1 18 <- [0x0000003030 - 0x0000003037] io
> PCI: 00:05.1 1c <- [0x00000030b0 - 0x00000030b3] io
> PCI: 00:05.1 20 <- [0x0000002ce0 - 0x0000002cef] io
> PCI: 00:05.1 24 <- [0x00f2247000 - 0x00f2247fff] mem
>
> pci_dev_set_resources(struct device *dev)
> PCI: 00:05.2 10 <- [0x0000003040 - 0x0000003047] io
> PCI: 00:05.2 14 <- [0x00000030c0 - 0x00000030c3] io
> PCI: 00:05.2 18 <- [0x0000003050 - 0x0000003057] io
> PCI: 00:05.2 1c <- [0x00000030d0 - 0x00000030d3] io
> PCI: 00:05.2 20 <- [0x0000002cf0 - 0x0000002cff] io
> PCI: 00:05.2 24 <- [0x00f2248000 - 0x00f2248fff] mem
>
> pci_dev_set_resources(struct device *dev)
> PCI: 00:06.0 1c <- [0x0000001000 - 0x0000001fff] bus 01 io
> PCI: 00:06.0 20 <- [0x00f2100000 - 0x00f21fffff] bus 01 mem
>
> pci_dev_set_resources(struct device *dev)
> PCI: 01:00.0 10 <- [0x0000001880 - 0x000000188f] io
> PCI: 01:00.0 14 <- [0x00f2110000 - 0x00f21107ff] mem
> PCI: 01:00.0 30 <- [0x00f2111000 - 0x00f21117ff] romem
>
> pci_dev_set_resources(struct device *dev)
> PCI: 01:01.0 10 <- [0x0000001000 - 0x00000010ff] io
> PCI: 01:01.0 30 <- [0x00f2100000 - 0x00f2107fff] romem
>
> pci_dev_set_resources(struct device *dev)
> PCI: 01:02.0 10 <- [0x0000001400 - 0x00000014ff] io
> PCI: 01:02.0 30 <- [0x00f2108000 - 0x00f210ffff] romem
>
> pci_dev_set_resources(struct device *dev)
> PCI: 01:04.0 10 <- [0x00f2112000 - 0x00f21127ff] mem
> PCI: 01:04.0 14 <- [0x0000001800 - 0x000000187f] io
>
> pci_dev_set_resources(struct device *dev)
> PCI: 00:06.1 10 <- [0x00f2240000 - 0x00f2243fff] mem
>
> pci_dev_set_resources(struct device *dev)
> PCI: 00:08.0 10 <- [0x00f2249000 - 0x00f2249fff] mem
> PCI: 00:08.0 14 <- [0x0000003060 - 0x0000003067] io
> PCI: 00:08.0 18 <- [0x00f224c000 - 0x00f224c0ff] mem
> PCI: 00:08.0 1c <- [0x00f224e000 - 0x00f224e00f] mem
>
> pci_dev_set_resources(struct device *dev)
> PCI: 00:09.0 10 <- [0x00f224a000 - 0x00f224afff] mem
> PCI: 00:09.0 14 <- [0x0000003070 - 0x0000003077] io
> PCI: 00:09.0 18 <- [0x00f224d000 - 0x00f224d0ff] mem
> PCI: 00:09.0 1c <- [0x00f224f000 - 0x00f224f00f] mem
>
> pci_dev_set_resources(struct device *dev)
> PCI: 00:0f.0 24 <- [0x00e0000000 - 0x00efffffff] bus 07 prefmem
> PCI: 00:0f.0 20 <- [0x00f0000000 - 0x00f20fffff] bus 07 mem
>
> pci_dev_set_resources(struct device *dev)
> PCI: 07:00.0 10 <- [0x00f0000000 - 0x00f0ffffff] mem
> PCI: 07:00.0 14 <- [0x00e0000000 - 0x00efffffff] prefmem64
> PCI: 07:00.0 1c <- [0x00f1000000 - 0x00f1ffffff] mem64
> PCI: 07:00.0 30 <- [0x00f2000000 - 0x00f201ffff] romem
> Done setting resources.
> Done allocating resources.
> Enabling resources...
> PCI: 00:18.0 cmd <- 140
> 0x55 status: 01
> PCI: 00:00.0 subsystem <- 1462/9282
> PCI: 00:00.0 cmd <- 146
> 0x55 status: 00
> PCI: 00:01.0 subsystem <- 1462/9282
> PCI: 00:01.0 cmd <- 14f
> 0x55 status: 5a
> mcp55 lpc decode:PNP: 002e.0, base=0x000003f0, end=0x000003f7
> mcp55 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff
> mcp55 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
> mcp55 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
> w83627ehg hwm smbus enabled
> mcp55 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000297
> PCI: 00:01.1 subsystem <- 1462/9282
> PCI: 00:01.1 cmd <- 141
> 0x55 status: 00
> PCI: 00:01.2 cmd <- 540
> 0x55 status: 00
> PCI: 00:01.3 cmd <- 142
> 0x55 status: 00
> PCI: 00:02.0 subsystem <- 1462/9282
> PCI: 00:02.0 cmd <- 142
> 0x55 status: 47
> PCI: 00:02.1 subsystem <- 1462/9282
> PCI: 00:02.1 cmd <- 142
> 0x55 status: 00
> PCI: 00:04.0 subsystem <- 1462/9282
> PCI: 00:04.0 cmd <- 141
> 0x55 status: 00
> PCI: 00:05.0 subsystem <- 1462/9282
> PCI: 00:05.0 cmd <- 143
> 0x55 status: 00
> PCI: 00:05.1 subsystem <- 1462/9282
> PCI: 00:05.1 cmd <- 143
> 0x55 status: 00
> PCI: 00:05.2 subsystem <- 1462/9282
> PCI: 00:05.2 cmd <- 143
> 0x55 status: 00
> PCI: 00:06.0 bridge ctrl <- 0a03
> PCI: 00:06.0 cmd <- 147
> 0x55 status: 00
> PCI: 01:00.0 cmd <- 1c3
> 0x55 status: 00
> PCI: 01:01.0 cmd <- 143
> 0x55 status: 00
> PCI: 01:02.0 cmd <- 143
> 0x55 status: 00
> PCI: 01:04.0 cmd <- 1c3
> 0x55 status: 00
> PCI: 00:06.1 subsystem <- 1462/9282
> PCI: 00:06.1 cmd <- 142
> 0x55 status: 00
> PCI: 00:08.0 subsystem <- 1462/9282
> PCI: 00:08.0 cmd <- 143
> 0x55 status: 00
> PCI: 00:09.0 subsystem <- 1462/9282
> PCI: 00:09.0 cmd <- 143
> 0x55 status: 00
> PCI: 00:0a.0 bridge ctrl <- 0003
> PCI: 00:0a.0 cmd <- 140
> 0x55 status: 00
> PCI: 00:0b.0 bridge ctrl <- 0003
> PCI: 00:0b.0 cmd <- 140
> 0x55 status: 00
> PCI: 00:0c.0 bridge ctrl <- 0003
> PCI: 00:0c.0 cmd <- 140
> 0x55 status: 00
> PCI: 00:0d.0 bridge ctrl <- 0003
> PCI: 00:0d.0 cmd <- 140
> 0x55 status: 00
> PCI: 00:0e.0 bridge ctrl <- 0003
> PCI: 00:0e.0 cmd <- 140
> 0x55 status: 00
> PCI: 00:0f.0 bridge ctrl <- 000b
> PCI: 00:0f.0 cmd <- 147
> 0x55 status: 00
> PCI: 07:00.0 cmd <- 143
> 0x55 status: 00
> PCI: 00:18.1 subsystem <- 1462/9282
> PCI: 00:18.1 cmd <- 140
> 0x55 status: 00
> PCI: 00:18.2 subsystem <- 1462/9282
> PCI: 00:18.2 cmd <- 140
> 0x55 status: 00
> PCI: 00:18.3 cmd <- 140
> 0x55 status: 00
> done.
> Initializing devices...
> Root Device init
> APIC_CLUSTER: 0 init
> start_eip=0x00007000, offset=0x00110000, code_size=0x0000005b
> Initializing CPU #0
> CPU: vendor AMD device 40f32
> CPU: family 0f, model 43, stepping 02
> Enabling cache
>
> Setting fixed MTRRs(0-88) type: UC
> Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
> start_mtrr00000000
> last_mtrr00000010
> Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
> start_mtrr00000018
> last_mtrr00000058
> DONE fixed MTRRs
> Setting variable MTRR 0, base:    0MB, range: 1024MB, type WB
> DONE variable MTRRs
> Clear out the extra MTRR's
>
> MTRR check
> Fixed MTRRs   : Enabled
> Variable MTRRs: Enabled
>
> CPU model AMD Athlon(tm) 64 X2 Dual Core Processor 3800+
> Setting up local apic... apic_id: 0x00 done.
> ECC Disabled
> CPU #0 Initialized
> All AP CPUs stopped
> PCI: 00:18.0 init
> PCI: 00:01.0 init
> set power off after power fail
> RTC Init
> RTC: Checksum invalid zeroing cmos
> Invalid CMOS LB checksum
> PNP: 002e.0 init
> PNP: 002e.2 init
> PNP: 002e.5 init
> PNP: 002e.a init
> PNP: 002e.b init
> PCI: 00:01.1 init
> PCI: 00:02.1 init
> PCI: 00:04.0 init
> IDE0
> PCI: 00:05.0 init
> SATA S \0x09SATA P
> PCI: 00:05.1 init
> SATA S \0x09SATA P
> PCI: 00:05.2 init
> SATA S \0x09SATA P
> PCI: 00:06.0 init
> dev_root mem base = 0x00e0000000
> [0x50] <-- 0xe0000000
> PCI: 00:06.1 init
> base = f2240000
> codec_mask = 01
> codec viddid: 10ec0883
> No verb!
> PCI: 00:08.0 init
> MCP55 MAC PHY ID 0x00070400 PHY ADDR 32
> PCI: 00:09.0 init
> MCP55 MAC PHY ID 0x00070400 PHY ADDR 1
> PCI: 00:0a.0 init
> PCI: 00:0b.0 init
> PCI: 00:0c.0 init
> PCI: 00:0d.0 init
> PCI: 00:0e.0 init
> PCI: 00:0f.0 init
> PCI: 00:18.1 init
> PCI: 00:18.2 init
> PCI: 00:18.3 init
> NB: Function 3 Misc Control.. done.
> PCI: 00:01.2 init
> PCI: 00:01.3 init
> PCI: 01:00.0 init
> rom address for PCI: 01:00.0 = f2111000
> dump_mem:
> f2111000: 55 aa 04 e9 fb 01 01 10 52 13 36 50 64 19 05 10
> f2111010: 20 02 00 00 00 00 00 00 1e 00 36 00 00 00 50 43
> f2111020: 49 52 95 17 03 00 00 00 18 00 00 ff 00 00 04 00
> f2111030: 00 00 00 80 00 00 24 50 6e 50 01 02 00 00 00 dd
> f2111040: 95 17 03 00 6e 00 8e 01 ff 00 00 40 01 02 00 00
> f2111050: 00 00 00 00 00 00 0d 0a 41 63 63 65 73 73 20 73
> f2111060: 79 73 74 65 6d 20 42 49 4f 53 20 56 00 2e 20 43
> f2111070: 6f 70 79 72 69 67 68 74 20 28 43 29 20 4f 4b 42
> f2111080: 20 53 41 50 52 20 31 39 39 33 2d 32 30 30 36 00
> f2111090: 20 73 2f 6e 20 00 0d 0a 00 0d 0a 3f 41 43 43 4f
> f21110a0: 52 44 20 42 49 4f 53 2d 00 46 41 54 41 4c 2d 00
> f21110b0: 0d 0a 53 79 73 74 65 6d 20 68 61 6c 74 65 64 00
> f21110c0: 52 65 73 65 74 20 68 61 72 64 77 61 72 65 2e 2e
> f21110d0: 2e 00 0d 0a 4c 6f 61 64 69 6e 67 20 69 6d 61 67
> f21110e0: 65 2e 2e 2e 00 47 65 74 74 69 6e 67 20 73 2f 6e
> f21110f0: 2e 2e 2e 00 4f 4b 0d 0a 00 53 65 61 72 63 68 69
> header signature aa55
> Class Code mismatch ROM 000000ff, dev 00ff0000
> copying non-VGA ROM Image from 0xf2111000 to 0xd0000, 0x800 bytes
> dump_mem:
> 000d0000: 55 aa 04 e9 fb 01 01 10 52 13 36 50 64 19 05 10
> 000d0010: 20 02 00 00 00 00 00 00 1e 00 36 00 00 00 50 43
> 000d0020: 49 52 95 17 03 00 00 00 18 00 00 ff 00 00 04 00
> 000d0030: 00 00 00 80 00 00 24 50 6e 50 01 02 00 00 00 dd
> 000d0040: 95 17 03 00 6e 00 8e 01 ff 00 00 40 01 02 00 00
> 000d0050: 00 00 00 00 00 00 0d 0a 41 63 63 65 73 73 20 73
> 000d0060: 79 73 74 65 6d 20 42 49 4f 53 20 56 00 2e 20 43
> 000d0070: 6f 70 79 72 69 67 68 74 20 28 43 29 20 4f 4b 42
> 000d0080: 20 53 41 50 52 20 31 39 39 33 2d 32 30 30 36 00
> 000d0090: 20 73 2f 6e 20 00 0d 0a 00 0d 0a 3f 41 43 43 4f
> 000d00a0: 52 44 20 42 49 4f 53 2d 00 46 41 54 41 4c 2d 00
> 000d00b0: 0d 0a 53 79 73 74 65 6d 20 68 61 6c 74 65 64 00
> 000d00c0: 52 65 73 65 74 20 68 61 72 64 77 61 72 65 2e 2e
> 000d00d0: 2e 00 0d 0a 4c 6f 61 64 69 6e 67 20 69 6d 61 67
> 000d00e0: 65 2e 2e 2e 00 47 65 74 74 69 6e 67 20 73 2f 6e
> 000d00f0: 2e 2e 2e 00 4f 4b 0d 0a 00 53 65 61 72 63 68 69
> dump_mem:
> 000d1000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d1010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d1020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d1030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d1040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d1050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d1060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d1070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d1080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d1090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d10a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d10b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d10c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d10d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d10e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d10f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> entering emulator
> 0000:7004: 22 ILLEGAL EXTENDED X86 OPCODE!
> halt_sys: file 
> /root/Linuxbios/LinuxBIOSv2/src/devices/emulator/x86emu/ops2.c, line 60
> PCI: 01:01.0 init
> rom address for PCI: 01:01.0 = f2100000
> dump_mem:
> f2100000: 55 aa 40 eb 6e 00 00 00 00 00 00 00 00 00 00 00
> f2100010: 00 00 00 00 00 00 00 00 50 00 30 00 00 00 00 00
> f2100020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f2100030: 24 50 6e 50 01 02 00 00 00 81 72 11 12 f0 6d 00
> f2100040: 68 00 00 00 10 e0 00 00 00 00 00 00 00 00 00 00
> f2100050: 50 43 49 52 72 11 12 f0 00 00 18 00 00 00 00 10
> f2100060: 40 00 01 00 00 80 00 00 53 49 41 33 00 41 6e 63
> f2100070: 75 64 00 1e 06 66 60 fc 0e 1f 0e 07 8b d8 be aa
> f2100080: 01 e8 16 01 bf 10 00 b8 0a b1 cd 1a 0f 82 81 00
> f2100090: 0a e4 75 7d 8b d1 81 e2 fc ff 74 75 80 c2 14 33
> f21000a0: db b9 08 01 bf 00 02 8b f7 e8 9c 00 be a0 02 80
> f21000b0: 3c 00 74 5d 80 3c ff 74 58 e8 de 00 bf 00 02 8b
> f21000c0: f7 80 c2 0c b0 01 66 c1 e0 1d 66 ef 80 c2 08 b9
> f21000d0: 06 00 f3 6e 80 c2 f8 66 33 c0 66 ef 80 c2 f4 8b
> f21000e0: 1e 48 02 8b 0e 4c 02 e3 0d bf 00 02 e8 59 00 8a
> f21000f0: 0e 02 00 e8 0a 01 88 0e 02 00 c1 e1 ff ff ff ff
> header signature aa55
> Class Code mismatch ROM 00100000, dev 00020000
> copying non-VGA ROM Image from 0xf2100000 to 0xd0800, 0x8000 bytes
> dump_mem:
> 000d0000: 55 aa 04 e9 fb 01 01 10 52 13 36 50 64 19 05 10
> 000d0010: 20 02 00 00 00 00 00 00 1e 00 36 00 00 00 50 43
> 000d0020: 49 52 95 17 03 00 00 00 18 00 00 ff 00 00 04 00
> 000d0030: 00 00 00 80 00 00 24 50 6e 50 01 02 00 00 00 dd
> 000d0040: 95 17 03 00 6e 00 8e 01 ff 00 00 40 01 02 00 00
> 000d0050: 00 00 00 00 00 00 0d 0a 41 63 63 65 73 73 20 73
> 000d0060: 79 73 74 65 6d 20 42 49 4f 53 20 56 00 2e 20 43
> 000d0070: 6f 70 79 72 69 67 68 74 20 28 43 29 20 4f 4b 42
> 000d0080: 20 53 41 50 52 20 31 39 39 33 2d 32 30 30 36 00
> 000d0090: 20 73 2f 6e 20 00 0d 0a 00 0d 0a 3f 41 43 43 4f
> 000d00a0: 52 44 20 42 49 4f 53 2d 00 46 41 54 41 4c 2d 00
> 000d00b0: 0d 0a 53 79 73 74 65 6d 20 68 61 6c 74 65 64 00
> 000d00c0: 52 65 73 65 74 20 68 61 72 64 77 61 72 65 2e 2e
> 000d00d0: 2e 00 0d 0a 4c 6f 61 64 69 6e 67 20 69 6d 61 67
> 000d00e0: 65 2e 2e 2e 00 47 65 74 74 69 6e 67 20 73 2f 6e
> 000d00f0: 2e 2e 2e 00 4f 4b 0d 0a 00 53 65 61 72 63 68 69
> dump_mem:
> 000d1000: 55 aa 40 eb 6e 00 00 00 00 00 00 00 00 00 00 00
> 000d1010: 00 00 00 00 00 00 00 00 50 00 30 00 00 00 00 00
> 000d1020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d1030: 24 50 6e 50 01 02 00 00 00 81 72 11 12 f0 6d 00
> 000d1040: 68 00 00 00 10 e0 00 00 00 00 00 00 00 00 00 00
> 000d1050: 50 43 49 52 72 11 12 f0 00 00 18 00 00 00 00 10
> 000d1060: 40 00 01 00 00 80 00 00 53 49 41 33 00 41 6e 63
> 000d1070: 75 64 00 1e 06 66 60 fc 0e 1f 0e 07 8b d8 be aa
> 000d1080: 01 e8 16 01 bf 10 00 b8 0a b1 cd 1a 0f 82 81 00
> 000d1090: 0a e4 75 7d 8b d1 81 e2 fc ff 74 75 80 c2 14 33
> 000d10a0: db b9 08 01 bf 00 02 8b f7 e8 9c 00 be a0 02 80
> 000d10b0: 3c 00 74 5d 80 3c ff 74 58 e8 de 00 ff 00 ff ff
> 000d10c0: f7 80 c2 0c b0 01 66 c1 e0 1d 66 ef 80 c2 08 b9
> 000d10d0: 06 00 f3 6e 80 c2 f8 66 33 c0 66 ef ff ff ff ff
> 000d10e0: 1e 48 02 8b 0e 4c 02 e3 0d bf 00 02 ff ff ff ff
> 000d10f0: 0e 02 00 e8 ff ff ff ff ff ff ff ff ff ff ff ff
> entering emulator
> 0000:7004: 22 ILLEGAL EXTENDED X86 OPCODE!
> halt_sys: file 
> /root/Linuxbios/LinuxBIOSv2/src/devices/emulator/x86emu/ops2.c, line 60
> PCI: 01:02.0 init
> rom address for PCI: 01:02.0 = f2108000
> dump_mem:
> f2108000: 55 aa 40 eb 6e 00 00 00 00 00 00 00 00 00 00 00
> f2108010: 00 00 00 00 00 00 00 00 50 00 30 00 00 00 00 00
> f2108020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f2108030: 24 50 6e 50 01 02 00 00 00 81 72 11 12 f0 6d 00
> f2108040: 68 00 00 00 10 e0 00 00 00 00 00 00 00 00 00 00
> f2108050: 50 43 49 52 72 11 12 f0 00 00 18 00 00 00 00 10
> f2108060: 40 00 01 00 00 80 00 00 53 49 41 33 00 41 6e 63
> f2108070: 75 64 00 1e 06 66 60 fc 0e 1f 0e 07 8b d8 be aa
> f2108080: 01 e8 16 01 bf 10 00 b8 0a b1 cd 1a 0f 82 81 00
> f2108090: 0a e4 75 7d 8b d1 81 e2 fc ff 74 75 80 c2 14 33
> f21080a0: db b9 08 01 bf 00 02 8b f7 e8 9c 00 be a0 02 80
> f21080b0: 3c 00 74 5d 80 3c ff 74 58 e8 de 00 bf 00 02 8b
> f21080c0: f7 80 c2 0c b0 01 66 c1 e0 1d 66 ef 80 c2 08 b9
> f21080d0: 06 00 f3 6e 80 c2 f8 66 33 c0 66 ef 80 c2 f4 8b
> f21080e0: 1e 48 02 8b 0e 4c 02 e3 0d bf 00 02 e8 59 00 8a
> f21080f0: 0e 02 00 e8 0a 01 88 0e 02 00 c1 e1 09 74 0c 33
> header signature aa55
> Class Code mismatch ROM 00100000, dev 00020000
> copying non-VGA ROM Image from 0xf2108000 to 0xd8800, 0x8000 bytes
> dump_mem:
> 000d0000: 08 09 0a e9 fb 01 01 10 52 13 36 50 64 19 05 10
> 000d0010: 20 02 00 00 00 00 00 00 1e 00 36 00 00 00 50 43
> 000d0020: 49 52 95 17 03 00 00 00 18 00 00 ff 00 00 04 00
> 000d0030: 00 00 00 80 00 00 24 50 6e 50 01 02 00 00 00 dd
> 000d0040: 95 17 03 00 6e 00 8e 01 ff 00 00 40 01 02 00 00
> 000d0050: 00 00 00 00 00 00 0d 0a 41 63 63 65 73 73 20 73
> 000d0060: 79 73 74 65 6d 20 42 49 4f 53 20 56 00 2e 20 43
> 000d0070: 6f 70 79 72 69 67 68 74 20 28 43 29 20 4f 4b 42
> 000d0080: 20 53 41 50 52 20 31 39 39 33 2d 32 30 30 36 00
> 000d0090: 20 73 2f 6e 20 00 0d 0a 00 0d 0a 3f 41 43 43 4f
> 000d00a0: 52 44 20 42 49 4f 53 2d 00 46 41 54 41 4c 2d 00
> 000d00b0: 0d 0a 53 79 73 74 65 6d 20 68 61 6c 74 65 64 00
> 000d00c0: 52 65 73 65 74 20 68 61 72 64 77 61 72 65 2e 2e
> 000d00d0: 2e 00 0d 0a 4c 6f 61 64 69 6e 67 20 69 6d 61 67
> 000d00e0: 65 2e 2e 2e 00 47 65 74 74 69 6e 67 20 73 2f 6e
> 000d00f0: 2e 2e 2e 00 4f 4b 0d 0a 00 53 65 61 72 63 68 69
> dump_mem:
> 000d1000: 55 aa 40 eb 6e 00 c7 87 00 00 00 00 00 00 00 00
> 000d1010: 00 00 00 00 00 00 00 00 50 00 30 00 00 00 00 00
> 000d1020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 000d1030: 24 50 6e 50 01 02 00 00 00 81 72 11 12 f0 6d 00
> 000d1040: 68 00 00 00 10 e0 00 00 00 00 00 00 00 00 00 00
> 000d1050: 50 43 49 52 72 11 12 f0 00 00 18 00 00 00 00 10
> 000d1060: 40 00 01 00 00 80 00 00 53 49 41 33 00 41 6e 63
> 000d1070: 75 64 00 1e 06 66 60 fc 0e 1f 0e 07 8b d8 be aa
> 000d1080: 01 e8 16 01 bf 10 00 b8 0a b1 cd 1a 0f 82 81 00
> 000d1090: 0a e4 75 7d 8b d1 81 e2 fc ff 74 75 80 c2 14 33
> 000d10a0: db b9 08 01 bf 00 02 8b f7 e8 9c 00 be a0 02 80
> 000d10b0: 3c 00 74 5d 80 3c ff 74 58 e8 de 00 ff 00 ff ff
> 000d10c0: f7 80 c2 0c b0 01 66 c1 e0 1d 66 ef 80 c2 08 b9
> 000d10d0: 06 00 f3 6e 80 c2 f8 66 33 c0 66 ef ff ff ff ff
> 000d10e0: 1e 48 02 8b 0e 4c 02 e3 0d bf 00 02 ff ff ff ff
> 000d10f0: 0e 02 00 e8 ff ff ff ff ff ff ff ff ff ff ff ff
> entering emulator
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> un-inited int vector
> halt_sys: file 
> /root/Linuxbios/LinuxBIOSv2/src/devices/emulator/x86emu/ops.c, line 4387
> PCI: 01:04.0 init
> PCI: 07:00.0 init
> rom address for PCI: 07:00.0 = f2000000
> dump_mem:
> f2000000: 55 aa 7e eb 4b 37 34 30 30 e9 4c 19 77 cc 56 49
> f2000010: 44 45 4f 20 0d 00 00 00 08 01 79 11 00 00 49 42
> f2000020: 4d 20 56 47 41 20 43 6f 6d 70 61 74 69 62 6c 65
> f2000030: 01 00 00 00 80 10 86 99 31 30 2f 32 34 2f 30 36
> f2000040: 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00
> f2000050: e9 77 dd 00 43 10 1d 82 ff cf ef 7f 00 10 00 80
> f2000060: ff ff ff 7f 00 00 00 80 22 00 a5 71 e9 4d b8 e9
> f2000070: 54 b8 50 4d 49 44 6c 00 6f 00 00 00 00 a0 00 b0
> f2000080: 00 b8 00 c0 00 33 7e ca 9b 00 02 00 04 00 6a 21
> f2000090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> f20000a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> f20000b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> f20000c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> f20000d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> f20000e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> f20000f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> header signature aa55
> copying VGA ROM Image from 0xf2000000 to 0xc0000, 0xfc00 bytes
> dump_mem:
> 000c0000: 55 aa 7e eb 4b 37 34 30 30 e9 4c 19 77 cc 56 49
> 000c0010: 44 45 4f 20 0d 00 00 00 08 01 79 11 00 00 49 42
> 000c0020: 4d 20 56 47 41 20 43 6f 6d 70 61 74 69 62 6c 65
> 000c0030: 01 00 00 00 80 10 86 99 31 30 2f 32 34 2f 30 36
> 000c0040: 00 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00
> 000c0050: e9 77 dd 00 43 10 1d 82 ff cf ef 7f 00 10 00 80
> 000c0060: ff ff ff 7f 00 00 00 80 22 00 a5 71 e9 4d b8 e9
> 000c0070: 54 b8 50 4d 49 44 6c 00 6f 00 00 00 00 a0 00 b0
> 000c0080: 00 b8 00 c0 00 33 7e ca 9b 00 02 00 04 00 6a 21
> 000c0090: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 000c00a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 000c00b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 000c00c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 000c00d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 000c00e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 000c00f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
> 000c0100: ff ff ff ff 48 57 45 41 50 43 49 52 de 10 d1 01
> 000c0110: 00 00 18 00 00 00 00 03 7e 00 01 00 00 80 00 00
> 000c0120: 41 53 55 53 20 45 4e 37 33 30 30 54 43 35 31 32
> 000c0130: 20 56 47 41 20 42 49 4f 53 20 56 65 72 73 69 6f
> 000c0140: 6e 20 35 2e 37 32 2e 32 32 2e 34 33 2e 41 53 32
> 000c0150: 39 0d 0a 00 44 4a 48 01 c2 01 90 01 14 28 14 28
> 000c0160: 45 4e 37 33 30 30 54 43 35 31 32 00 00 00 00 00
> 000c0170: 00 56 65 72 73 69 6f 6e 20 20 35 2e 37 32 2e 32
> 000c0180: 32 2e 34 33 2e 30 30 20 0d 0a 00 43 6f 70 79 72
> 000c0190: 69 67 68 74 20 28 43 29 20 31 39 39 36 2d 32 30
> 000c01a0: 30 36 20 4e 56 49 44 49 41 20 43 6f 72 70 2e 0d
> 000c01b0: 0a 00 00 00 ba 91 98 96 91 9a 9a 8d 96 91 98 df
> 000c01c0: ad 9a 93 9a 9e 8c 9a df d2 df b1 90 8b df b9 90
> 000c01d0: 8d df af 8d 90 9b 8a 9c 8b 96 90 91 df aa 8c 9a
> 000c01e0: f2 f5 ff ff ff 47 37 32 20 42 6f 61 72 64 20 2d
> 000c01f0: 20 70 33 38 31 6e 30 20 20 00 00 00 00 00 00 00
> 000c0200: 00 00 00 00 00 00 00 00 43 68 69 70 20 52 65 76
> 000c0210: 20 20 20 00 00 00 00 00 00 00 00 00 ff b8 42 49
> 000c0220: 54 00 00 01 0c 06 11 46 32 01 04 00 8e 02 42 02
> 000c0230: 19 00 92 02 43 01 0e 00 ab 02 44 01 04 00 b9 02
> 000c0240: 49 01 0e 00 bd 02 4c 01 02 00 cb 02 74 01 12 00
> 000c0250: cd 02 4d 01 0d 00 df 02 4e 00 00 00 00 00 50 01
> 000c0260: 19 00 ec 02 53 02 15 00 05 03 54 01 02 00 1a 03
> 000c0270: 55 01 03 00 1c 03 56 01 06 00 1f 03 63 00 00 00
> 000c0280: 00 00 69 02 25 00 25 03 73 01 10 00 4a 03 00 00
> 000c0290: 00 00 43 22 72 05 00 00 00 00 00 00 a8 07 00 00
> 000c02a0: 00 00 00 00 00 00 02 04 55 55 00 00 00 00 00 00
> 000c02b0: 00 00 00 96 5d ba 30 31 5f a8 96 de 96 10 60 22
> 000c02c0: 60 2a 60 4a 60 7a 60 7a 60 22 60 04 d1 3a cf 40
> 000c02d0: cf 46 cf 5e cf 76 cf 8e cf a6 cf be cf d6 cf cb
> 000c02e0: 60 08 ff 5f 00 00 00 00 00 00 00 00 64 df 00 00
> 000c02f0: 66 e0 00 00 00 00 00 00 29 df 00 00 c6 e0 00 00
> entering emulator
> halt_sys: file 
> /root/Linuxbios/LinuxBIOSv2/src/devices/emulator/x86emu/ops.c, line 4387
> Devices initialized
> Writing IRQ routing tables to 0xf0000...done.
> Assigning IRQ 3 to 0:6.1
>   Readback = 3
> Assigning IRQ 11 to 0:1.1
>   Readback = 11
> Assigning IRQ 11 to 0:1.3
>   Readback = 11
> Assigning IRQ 10 to 0:8.0
>   Readback = 10
> Assigning IRQ 10 to 0:9.0
>   Readback = 10
> Assigning IRQ 7 to 0:5.0
>   Readback = 7
> Assigning IRQ 10 to 0:5.1
>   Readback = 10
> Assigning IRQ 11 to 0:5.2
>   Readback = 11
> Assigning IRQ 10 to 7:0.0
>   Readback = 10
> Assigning IRQ 11 to 1:0.0
>   Readback = 11
> Assigning IRQ 11 to 1:1.0
>   Readback = 11
> Assigning IRQ 7 to 1:2.0
>   Readback = 7
> smp_write_processor
> cpu->path.u.apic.apic_id
> 00apic_version
> 10cpu_flag
> 03cpu_features
> 00040f32cpu_feature_flags
> 178bfbffDevice found
> PCI: 0011c2a0f2244000
> bus_isa 00000008
> bus_mcp55[0] 00000000
> bus_mcp55[1] 00000001
> apicid_mcp55 00000001
> Wrote the mp table end at: 00000020 - 00000270
> Moving GDT to 0x500...ok
> Adjust low_table_end from 0x00000530 to 0x00001000
> Adjust rom_table_end from 0x000f0400 to 0x00100000
> Wrote linuxbios table at: 00000530 - 00000db4  checksum fc15
>
> Welcome to elfboot, the open sourced starter.
> January 2002, Eric Biederman.
> Version 1.3
>
> rom_stream: 0xfff80000 - 0xfff9ffff
> Found ELF candidate at offset 0
> header_offset is 0
> Try to load at offset 0x0
> New segment addr 0x100000 size 0x23ea0 offset 0xc0 filesize 0x9e28
> (cleaned up) New segment addr 0x100000 size 0x23ea0 offset 0xc0 
> filesize 0x9e28
> New segment addr 0x1s23ea0 size 0x48egment addr 0x123ea0 size 0x48 
> offset 0x9f00 filesize 0x48
> Dropping non PT_LOAD segment
> Dropping non PT_LOAD segment
> Loading Segment: addr: 0x000000003ff7c000 memsz: 0x0000000000023ea0 
> filesz: 0x0000000000009e28
> Clearing Segment: addr: 0x000000003ff85e28 memsz: 0x000000000001a078
> Loading Segment: addr: 0x000000003ff9fea0 memsz: 0x0000000000000048 
> filesz: 0x0000000000000048
> Jumping to boot code at 0x107b1c
> .....
>
> Here starts filo, and boots linux
> I will send a patch a bit later.
>
> I boot 2.4.21 kernel it works fine under stock BIOS is there any 
> chance to make this kernel work under LinuxBIOS?
>
> Best Regards,
>
> George.

diff -Naur ms9282/Config.lb ms7250/Config.lb
--- ms9282/Config.lb	2008-01-26 16:57:03.000000000 +0000
+++ ms7250/Config.lb	2007-09-26 13:49:54.000000000 +0000
@@ -1,5 +1,5 @@
 ##
-## This file is part of the coreboot project.
+## This file is part of the LinuxBIOS project.
 ##
 ## Copyright (C) 2006 AMD
 ## Written by Yinghai Lu  for AMD.
@@ -24,7 +24,7 @@

##
 ## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
        default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -36,19 +36,19 @@

##
 ## Compute the start location and size size of
-## The coreboot bootloader.
+## The linuxBIOS bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default CONFIG_ROM_PAYLOAD     = 1

##
-## Compute where this copy of coreboot will start in the boot rom
+## Compute where this copy of linuxBIOS will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )

##
-## Compute a range of ROM that can cached to speed up coreboot,
+## Compute a range of ROM that can cached to speed up linuxBIOS,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -81,14 +81,14 @@

makerule ./auto.o
         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
 end

else

makerule ./auto.inc
         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
        action "perl -e 's/.text/.section .rom.text/g' -pi $@"
 end
@@ -122,7 +122,7 @@
 end

##
-## Build our 16 bit and 32 bit coreboot entry code
+## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -142,7 +142,7 @@
 end

##
-## Build our reset vector (This is where coreboot is entered)
+## Build our reset vector (This is where linuxBIOS is entered)
 ##
 if USE_FALLBACK_IMAGE
        mainboardinit cpu/x86/16bit/reset16.inc
@@ -180,7 +180,7 @@
 end

###
-### This is the early phase of coreboot startup
+### This is the early phase of linuxBIOS startup
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
@@ -227,22 +227,21 @@
 end

-# sample config for msi/ms9282
+# sample config for msi/ms7250
 chip northbridge/amd/amdk8/root_complex
         device apic_cluster 0 on
-                chip cpu/amd/socket_F
+                chip cpu/amd/socket_AM2
                         device apic 0 on end
                 end
         end
-
-       device pci_domain 0 on
-               chip northbridge/amd/amdk8 #mc0
-                       device pci 18.0 on #  northbridge
-                               #  devices on link 0, link 0 == LDT 0
-                               chip southbridge/nvidia/mcp55
-                                       device pci 0.0 on end   # HT
-                                       device pci 1.0 on # LPC
-                                               chip superio/winbond/w83627ehg
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on 
+				#  devices on link 0, link 0 == LDT 0 
+			        chip southbridge/nvidia/mcp55 
+					device pci 0.0 on end   # HT
+                			device pci 1.0 on # LPC was 1.0 test
+						chip superio/winbond/w83627ehg
                                                        device pnp 2e.0 on #  Floppy
                                                                io 0x60 = 0x3f0
                                                                irq 0x70 = 6
@@ -276,106 +275,86 @@
                                                        end
                                                        device pnp 2e.8 off end #  WDTO_PLED
                                                        device pnp 2e.9 off end #  GPIO2_GPIO3_GPIO4_GPIO5
-                                                       device pnp 2e.a off end #  ACPI
+                                                       device pnp 2e.a on  end #  ACPI
                                                        device pnp 2e.b on #  HW Monitor
                                                                io 0x60 = 0x290
                                                                irq 0x70 = 5
                                                        end
                                                end
-                                       end
-                                        device pci 1.1 on # SM 0
-                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
-                                                       device i2c 70 on  #0 pca9554 1
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 54 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 55 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 56 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 57 on end
-                                                                end
-                                                       end
-                                                       device i2c 70 on  #0 pca9554 2
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 54 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 55 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 56 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 57 on end
-                                                                end
-                                                       end
-                                               end
-                                       end
-                                       device pci 1.1 on # SM 1
-                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
-                                                       device i2c 72 on     #pca9554 channle1
-                                                               chip drivers/i2c/adm1027   #HWM ADT7476 1
-                                                                       device i2c 2e on end
-                                                               end
-                                                       end
-                                                       device i2c 72 on     #pca9545 channel 2
-                                                               chip drivers/i2c/adm1027   #HWM ADT7463
-                                                                       device i2c 2e on end
-                                                               end
-                                                       end
-                                                       device i2c 72 on end  #pca9545 channel 3
-                                                       device i2c 72 on      #pca9545 channel 4
-                                                               chip drivers/i2c/adm1027   #HWM ADT7476 2
-                                                                       device i2c 2e on end
-                                                               end
-                                                       end
-                                               end
-                                       end
-
-                                       device pci 2.0 on end # USB 1.1
-                                       device pci 2.1 on end # USB 2
-                                       device pci 4.0 on  end # IDE
-                                               device pci 5.0 on  end # SATA 0
-                                       device pci 5.1 on  end # SATA 1
-                                       device pci 5.2 on  end # SATA 2
-                                       device pci 6.0 on  #P2P
+					end
+			                device pci 1.1 on # SM 0 was 1.1 test!
+                                                chip drivers/generic/generic #dimm 0-0-0
+                                                        device i2c 50 on end  
+                                                end              
+                                                chip drivers/generic/generic #dimm 0-0-1
+                                                        device i2c 51 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 0-1-0
+                                                        device i2c 52 on end
+                                                end             
+                                                chip drivers/generic/generic #dimm 0-1-1
+                                                        device i2c 53 on end
+                                                end              
+                                                chip drivers/generic/generic #dimm 1-0-0
+                                                        device i2c 54 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-0-1
+                                                        device i2c 55 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-0
+                                                        device i2c 56 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-1
+                                                        device i2c 57 on end
+                                                end 
+					end # SM
+                                        device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+#                                                chip drivers/generic/generic #PCIXA Slot1
+#                                                        device i2c 50 on end
+#                                                end
+#                                                chip drivers/generic/generic #PCIXB Slot1
+#                                                        device i2c 51 on end
+#                                                end     
+#                                                chip drivers/generic/generic #PCIXB Slot2
+#                                                        device i2c 52 on end
+#                                                end             
+#                                                chip drivers/generic/generic #PCI Slot1
+#                                                        device i2c 53 on end
+#                                                end              
+#                                                chip drivers/generic/generic #Master MCP55 PCI-E
+#                                                        device i2c 54 on end
+#                                                end     
+#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
+#                                                        device i2c 55 on end
+#                                                end             
+                                                chip drivers/generic/generic #MAC EEPROM
+                                                        device i2c 51 on end
+                                                end 
+
+                                        end # SM 
+					device pci 2.0 on end # USB 1.1
+        	        		device pci 2.1 on end # USB 2
+                			device pci 4.0 on end # IDE
+	                		device pci 5.0 on end # SATA 0
+	                		device pci 5.1 on end # SATA 1
+	                		device pci 5.2 on end # SATA 2
+					
+                			device pci 6.0 on end # PCI
+					
+					device pci 6.0 on  #P2P
                                                chip drivers/pci/onboard
                                                        device pci 4.0 on end
                                                        register "rom_address" = "0xfff80000"
                                                end
-                                       end # P2P
-                                       device pci 7.0 on end # reserve
-                                       device pci 8.0 on end # MAC0
-                                       device pci 9.0 on end # MAC1
-                                       device pci a.0 on
+					end  
+					    
+        	        		device pci 6.1 on end # AZA
+	                		device pci 8.0 on end # NIC
+	                		device pci 9.0 on end # NIC
+        	       			#device pci a.0 on end # PCI E 5
+					
+					 device pci a.0 on
                                                device pci 0.0 on
                                                        chip drivers/pci/onboard
                                                                device pci 4.0 on end  #pci_E lan1
@@ -383,36 +362,46 @@
                                                        end
                                                end
                                        end # 0x376
-                                               device pci b.0 on  end # PCI E 0x374
-                                       device pci c.0 on  end
-                                       device pci d.0 on   #SAS
+					
+					
+        	       			device pci b.0 on end # PCI E 4
+                			device pci c.0 on end # PCI E 3
+                			#device pci d.0 on end # PCI E 2
+					
+					 device pci d.0 on   #SAS
                                                chip drivers/pci/onboard
                                                        device pci 0.0 on end
                                                end
                                        end # PCI E 1 0x378
-                                       device pci e.0 on end # PCI E 0 0x375
-                                       device pci f.0 on end   #PCI E 0x377  pci_E slot
-                                       register "ide0_enable" = "1"
-                                       register "ide1_enable" = "1"
-                                       register "sata0_enable" = "1"
-                                       register "sata1_enable" = "1"
-                               end
-                       end #  device pci 18.0
-                       device pci 18.0 on end # Link 1
-                       device pci 18.0 on end
-                       device pci 18.1 on end
-                       device pci 18.2 on end
-                       device pci 18.3 on end
-               end #mc0
-
-       end # pci_domain
-
-#        chip drivers/generic/debug
-#                device pnp 0.0 off end
-#                device pnp 0.1 off end
-#                device pnp 0.2 off end
-#                device pnp 0.3 off end
-#                device pnp 0.4 off end
-#              device pnp 0.5 on end
-#        end
-end # root_complex
+					
+                			device pci e.0 on end # PCI E 1
+        	       			device pci f.0 on end # PCI E 0
+	                                register "ide0_enable" = "1"
+                	                register "sata0_enable" = "1"
+                        	        register "sata1_enable" = "1"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 18.0 
+			device pci 18.0 on end # Link 1
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end # mc0
+		
+	end # PCI domain
+	
+#       chip drivers/generic/debug 
+#               device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 on end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 on end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#               device pnp 0.7 off end # tsc
+#                device pnp 0.8 off  end # io
+#                device pnp 0.9 off end # io
+#       end  
+end #root_complex
diff -Naur ms9282/Options.lb ms7250/Options.lb
--- ms9282/Options.lb	2008-01-18 15:08:58.000000000 +0000
+++ ms7250/Options.lb	2007-08-07 11:47:35.000000000 +0000
@@ -1,5 +1,5 @@
 ##
-## This file is part of the coreboot project.
+## This file is part of the LinuxBIOS project.
 ##
 ## Copyright (C) 2006 AMD
 ## Written by Yinghai Lu  for AMD.
@@ -57,7 +57,7 @@
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
+uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
 uses CONFIG_GDB_STUB
 uses CROSS_COMPILE
@@ -99,7 +99,6 @@
 # stepan 2007-04-12
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_PRECOMPRESSED_PAYLOAD

## ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes
@@ -125,7 +124,7 @@
 default HAVE_FALLBACK_BOOT=1

##
-## Build code to reset the motherboard from coreboot
+## Build code to reset the motherboard from linuxBIOS
 ##
 default HAVE_HARD_RESET=1

@@ -133,7 +132,7 @@
 ## Build code to export a programmable irq routing table
 ##
 default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
+default IRQ_SLOT_COUNT=23

##
 ## Build code to export an x86 MP table
@@ -147,7 +146,7 @@
 default HAVE_OPTION_TABLE=1

##
-## Move the default coreboot cmos range off of AMD RTC registers
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -158,8 +157,10 @@
 ## Only worry about 2 micro processors
 ##
 default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_MAX_CPUS=2
+## was 4
+default CONFIG_MAX_PHYSICAL_CPUS=1
+## was 2/1
 default CONFIG_LOGICAL_CPUS=1

#CHIP_NAME ?
@@ -181,7 +182,8 @@
 #bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2

##bx_b005+ make the SB HT chain on bus 0
-default SB_HT_CHAIN_ON_BUS0=1
+default SB_HT_CHAIN_ON_BUS0=2
+##was1

##only offset for SB chain?, default is yes(1)
 default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
@@ -194,14 +196,16 @@
 ## enable CACHE_AS_RAM specifics
 ##
 default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xcc000
-default DCACHE_RAM_SIZE=0x4000
+default DCACHE_RAM_BASE=0xc8000
+## was 0xcc000
+default DCACHE_RAM_SIZE=0x08000
+## was 0x4000
 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
 default CONFIG_USE_INIT=0

-default ENABLE_APIC_EXT_ID=1
+default ENABLE_APIC_EXT_ID=0
 default APIC_ID_OFFSET=0x10
-default LIFT_BSP_APIC_ID=0
+default LIFT_BSP_APIC_ID=1

##
@@ -212,16 +216,16 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="ms9282"
+default MAINBOARD_PART_NUMBER="ms7250"
 default MAINBOARD_VENDOR="MSI"
 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282

###
-### coreboot layout values
+### LinuxBIOS layout values
 ###

-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
 default ROM_IMAGE_SIZE = 65536

##
@@ -232,7 +236,8 @@
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default HEAP_SIZE=0x8000
+## was 0x4000

##
 ## Only use the option table in a normal image
@@ -240,9 +245,10 @@
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE

##
-## Coreboot C code runs at this location in RAM
+## LinuxBIOS C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default _RAMBASE=0x00100000
+### was 0x00004000

##
 ## Load the payload from the ROM
@@ -289,7 +295,7 @@
 default TTYS0_LCS=0x3

##
-### Select the coreboot loglevel
+### Select the linuxBIOS loglevel
 ##
 ## EMERG      1   system is unusable
 ## ALERT      2   action must be taken immediately
diff -Naur ms9282/apc_auto.c ms7250/apc_auto.c
--- ms9282/apc_auto.c	1970-01-01 00:00:00.000000000 +0000
+++ ms7250/apc_auto.c	2007-02-17 14:28:11.000000000 +0000
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu  for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+
+#define SET_NB_CFG_54 1 
+
+//used by raminit
+#define QRANK_DIMM_SUPPORT 1
+
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+
+#if CONFIG_USE_INIT == 0
+        #include "lib/memcpy.c"
+#endif
+
+#include "arch/i386/lib/console.c"
+
+#if 0 
+static void post_code(uint8_t value) {
+#if 1
+        int i;
+        for(i=0;i<0x80000;i++) {
+                outb(value, 0x80);
+        }
+#endif
+}
+#endif
+
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+
+#include "lib/delay.c"
+
+//#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+
+#include "northbridge/amd/amdk8/debug.c"
+
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+
+#include "northbridge/amd/amdk8/amdk8_f.h"
+
+#include "cpu/x86/mtrr.h"
+#include "cpu/amd/mtrr.h"
+#include "cpu/x86/tsc.h"
+
+#include "northbridge/amd/amdk8/amdk8_f_pci.c"
+#include "northbridge/amd/amdk8/raminit_f_dqs.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+void hardwaremain(int ret_addr)
+{
+	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
+        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+
+	struct node_core_id id;
+
+	id = get_node_core_id_x();
+
+	//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
+        print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+
+	train_ram(id.nodeid, sysinfo, sysinfox);
+
+	/*
+		go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
+	*/
+
+        __asm__ volatile (
+                "movl  %0, %%edi\n\t"
+                "jmp     *%%edi\n\t"
+                :: "a"(ret_addr)
+        );
+
+
+
+}
+struct eregs {
+        uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
+        uint32_t vector;
+        uint32_t error_code;
+        uint32_t eip;
+        uint32_t cs;
+        uint32_t eflags;
+};
+
+void x86_exception(struct eregs *info)
+{
+        do {
+                hlt();
+        } while(1);
+}
+
+
diff -Naur ms9282/cache_as_ram_auto.c ms7250/cache_as_ram_auto.c
--- ms9282/cache_as_ram_auto.c	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/cache_as_ram_auto.c	2007-07-10 15:49:38.000000000 +0000
@@ -1,12 +1,9 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2006 AMD
+ * Copyright (C) 2007 AMD
  * Written by Yinghai Lu  for AMD.
  *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi  for MSI.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -26,56 +23,80 @@
 #define __ROMCC__

#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0

-#define SET_NB_CFG_54 1
+#define K8_ALLOCATE_IO_RANGE 1
+//#define K8_SCAN_PCI_BUS 1
+

-//used by raminit
 #define QRANK_DIMM_SUPPORT 1

+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+
 //used by init_cpus and fidvid
 #define K8_SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1

-#define DEBUG_SMBUS 1
+#if K8_REV_F_SUPPORT == 1
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif

+#define DBGP_DEFAULT 7
+ 
 #include <stdint.h>
 #include <device/pci_def.h>
+#include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
+
+#if USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
+#if CONFIG_USBDEBUG_DIRECT
+#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
+#include "pc80/usbdebug_direct_serial.c"
+#endif
+#include "ram/ramtest.c"

#include <cpu/amd/model_fxx_rev.h>
+
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"

-#if CONFIG_USE_INIT == 0
-       #include "lib/memcpy.c"
 #endif

#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"

-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#if USE_FAILOVER_IMAGE==0
+
 #include "cpu/x86/bist.h"

+#if CONFIG_USE_INIT == 0
+        #include "lib/memcpy.c"
+#endif
+
+#include "northbridge/amd/amdk8/debug.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+
 #include "northbridge/amd/amdk8/setup_resource_map.c"

#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)

-#include <device/pci_ids.h>
+
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+
 static void memreset_setup(void)
 {
 }
@@ -86,49 +107,48 @@

static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
-#define SMBUS_SWITCH1 0x70
-#define SMBUS_SWITCH2 0x72
-        unsigned device=(ctrl->channel0[0])>>8;
-        smbus_send_byte(SMBUS_SWITCH1, device);
-       smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
+	print_debug("activate_spd_rom: nothing needs to be done \r\n");
 }

-#if 0
-static inline void change_i2c_mux(unsigned device)
-{
-#define SMBUS_SWITCH1 0x70
-#define SMBUS_SWITHC2 0x72
-        smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
-       smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
-}
-#endif
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
-       return smbus_read_byte(device, address);
+	return smbus_read_byte(device, address);
 }

-//#define K8_4RANK_DIMM_SUPPORT 1
+
+
+
+
+

#include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/raminit_f.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
+
 #include "northbridge/amd/amdk8/incoherent_ht.c"
+
+#include "northbridge/amd/amdk8/raminit_f.c"
+
 #include "sdram/generic_sdram.c"

- /* msi does not want the default */
-#include "resourcemap.c"
+#include "resourcemap.c" 
+
 #include "cpu/amd/dualcore/dualcore.c"

#define MCP55_NUM 1
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-//set GPIO to input mode
+#define MCP55_USE_NIC 1
+#define MCP55_USE_AZA 1
+
+#define MCP55_PCI_E_X_0 0
+
 #define MCP55_MB_SETUP \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */

+#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"

#include "cpu/amd/car/copy_and_run.c"
@@ -136,9 +156,12 @@
 #include "cpu/amd/car/post_cache_as_ram.c"

#include "cpu/amd/model_fxx/init_cpus.c"
+
 #include "cpu/amd/model_fxx/fidvid.c"

-#if USE_FALLBACK_IMAGE == 1
+#endif
+
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))

#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -151,16 +174,19 @@
         uint32_t dword;
         uint8_t byte;

-        byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20;
+        byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+        byte |= 0x20; 
         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
+        
         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
         dword |= (1<<0);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
-
+        
+        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
+        dword |= (1<<16);
+        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 }
+
 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 {
         unsigned last_boot_normal_x = last_boot_normal();
@@ -198,99 +224,180 @@
  normal_image:
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
-                : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
                 );

fallback_image:
-       ;
+#if HAVE_FAILOVER_BOOT==1
+        __asm__ volatile ("jmp __fallback_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                )
+#endif
+	;
 }
 #endif
-
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-
-#if USE_FALLBACK_IMAGE == 1
-        failover_process(bist, cpu_init_detectedx);
+#if HAVE_FAILOVER_BOOT==1 
+    #if USE_FAILOVER_IMAGE==1
+	failover_process(bist, cpu_init_detectedx);	
+    #else
+	real_main(bist, cpu_init_detectedx);
+    #endif
+#else
+    #if USE_FALLBACK_IMAGE == 1
+	failover_process(bist, cpu_init_detectedx);	
+    #endif
+	real_main(bist, cpu_init_detectedx);
 #endif
-        real_main(bist, cpu_init_detectedx);
-
 }

-//CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
-#define RC0 (2<<8)
-#define RC1 (1<<8)
+#if USE_FAILOVER_IMAGE==0

void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-       static const uint16_t spd_addr [] = {
-                       RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
-                       RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
+	static const uint16_t spd_addr [] = {
+			(0xa<<3)|0, (0xa<<3)|1, 0, 0,
+			(0xa<<3)|2, (0xa<<3)|3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-                       RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
-                       RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
+			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
+			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
 #endif
-       };
-
-       unsigned bsp_apicid = 0;
-        int needs_reset;
-       struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
-       char *p ;
+	};
+	
+	
+
+        struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+        int needs_reset = 0;
+        unsigned bsp_apicid = 0;
+	
+	uint32_t dword;

if (bist == 0) {
-               //init_cpus(cpu_init_detectedx);
-               bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+		
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+		
         }

-       w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
+	
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+	
+	if (bist == 0) {
+		print_debug("bist==0 cpus inited \r\n");
+		}
+		
+	#if CONFIG_MAX_PHYSICAL_CPUS > 1
+	print_debug("CONFIG_MAX_PHYSICAL_CPUS > 1 \r\n");
+	#endif
+
+
+#if CONFIG_USBDEBUG_DIRECT
+	mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
+	early_usbdebug_direct_init();
+	//console_init();
+#endif
+        //console_init();
+        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");

-       /* Halt if there was a built in self test failure */
-       report_bist_failure(bist);
-
-        setup_ms9282_resource_map();
+        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");

-       setup_coherent_ht_domain();
+        
+#if MEM_TRAIN_SEQ == 1
+        set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
+	print_debug("set_sysinfo_in_ram(0)");
+#endif
+        setup_coherent_ht_domain(); // routing table and start other core0

wait_all_core0_started();
-
+	print_debug("setup_coherent_ht_domain()");
 #if CONFIG_LOGICAL_CPUS==1
         // It is said that we should start core1 after all core0 launched
+        /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
+         * So here need to make sure last core0 is started, esp for two way system,
+         * (there may be apic id conflicts in that case)
+         */
         start_other_cores();
-        //wait_all_other_cores_started(bsp_apicid);
+        wait_all_other_cores_started(bsp_apicid);
+	print_debug("start_other_cores()");
 #endif
+
+        /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn

-       needs_reset = optimize_link_coherent_ht();
+#if K8_SET_FIDVID == 1

-       needs_reset |= optimize_link_incoherent_ht(sysinfo);
+        {
+                msr_t msr;
+                msr=rdmsr(0xc0010042);
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");

-        needs_reset |= mcp55_early_setup_x();
+        }
+
+        enable_fid_change();
+
+        enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+        init_fidvid_bsp(bsp_apicid);
+
+        // show final fid and vid
+        {
+                msr_t msr;
+                msr=rdmsr(0xc0010042);
+                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");

-               if (needs_reset) {
-                       print_info("ht reset -\r\n");
-                       soft_reset();
-               }
-
-        //It's the time to set ctrl now;
-        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
-       enable_smbus();
-
-#if 0
-        int i;
-        for(i=4;i<8;i++) {
-                change_i2c_mux(i);
-                dump_smbus_registers();
         }
 #endif

-       memreset_setup();
+        needs_reset |= optimize_link_coherent_ht();
+        needs_reset |= optimize_link_incoherent_ht(sysinfo);
+        needs_reset |= mcp55_early_setup_x();
+
+        // fidvid change will issue one LDTSTOP and the HT change will be effective too
+        if (needs_reset) {
+                print_info("ht reset -\r\n");
+            	soft_reset();
+        }
+        allow_all_aps_stop(bsp_apicid);
+print_debug("allow_all_aps_stop");
+        //It's the time to set ctrl in sysinfo now;
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+print_debug("fill_mem_ctrl");
+        enable_smbus(); 
+print_debug("enable_smbus()");
+        memreset_setup();
+print_debug("memreset_setup()");
+        //do we need apci timer, tsc...., only debug need it for better output
+        /* all ap stopped? */
+	
+        //init_timer(); // Need to use TMICT to synconize FID/VID was disabled!
+//print_debug("init_timer()");
+
+        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+print_debug("sdram_initialize \r\n ");
+/*print_debug("sysinfo \r\n ");
+dump_mem(0x000cf000, 0x000cf730);*/
+write32(0x00100000,0x12345678);
+write32(0xfffe0000,0x12345678 /*value*/);
+dump_mem(0xfffe0000, 0xfffe0000+0x100);
+dump_mem(0x00100000, 0x00100000+0x100);
+
+dword=read32(0x00100000);
+print_debug_hex32(dword);

-       sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);

-       post_cache_as_ram();
+
+        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+	print_debug("post_cache_as_ram()");

}
+
+
+#endif
diff -Naur ms9282/chip.h ms7250/chip.h
--- ms9282/chip.h	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/chip.h	2007-06-28 11:15:52.000000000 +0000
@@ -1,5 +1,5 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2006 MSI
  * Written by Bingxun Shi  for MSI.
@@ -19,9 +19,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

-extern struct chip_operations mainboard_msi_ms9282_ops;
+extern struct chip_operations mainboard_msi_ms7250_ops;

-struct mainboard_msi_ms9282_config {
+struct mainboard_msi_ms7250_config {
        int fixup_scsi;
        int fixup_vga;
 };
diff -Naur ms9282/failover.c ms7250/failover.c
--- ms9282/failover.c	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/failover.c	2007-06-29 13:23:13.000000000 +0000
@@ -1,5 +1,5 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2006 AMD
  * Written by Yinghai Lu  for AMD.
@@ -61,7 +61,17 @@

static unsigned long main(unsigned long bist)
 {
-        /* Make cerain my local apic is useable */
+        int i=0;
+	/* Make cerain my local apic is useable */
+	#if 0
+	print_debug("entering main");
+	for(i=0;i<10000;i++)
+	{
+	intel_chip_post_macro(0x01);
+	}
+	#endif
+	
+	
         enable_lapic();

/* Is this a cpu only reset? */
diff -Naur ms9282/get_bus_conf.c ms7250/get_bus_conf.c
--- ms9282/get_bus_conf.c	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/get_bus_conf.c	2007-08-08 12:14:08.000000000 +0000
@@ -1,12 +1,9 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2006 AMD
+ * Copyright (C) 2007 AMD
  * Written by Yinghai Lu  for AMD.
  *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi  for MSI.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -33,70 +30,48 @@

#include <cpu/amd/amdk8_sysconf.h>

-#include "mb_sysconf.h"

// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
+//busnum is default
+        unsigned char bus_isa;
+        unsigned char bus_mcp55[8]; //1
+        unsigned apicid_mcp55;
+

-unsigned pci1234x[] =
+unsigned pci1234x[] = 
 {        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
-        //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-        0x0000ff0,
+	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
         0x0000ff0,
-        0x0000ff0,
-//        0x0000ff0,
+//        0x0000ff0, //   ff0
+//        0x0000ff0, //   ff0
+//        0x0000ff0, //   ff0
 //        0x0000ff0,
 //        0x0000ff0,
 //        0x0000ff0,
 //        0x0000ff0
 };
-unsigned hcdnx[] =
+unsigned hcdnx[] = 
 { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
-       0x20202020,
-       0x20202020,
-        0x20202020,
+	0x20202020,
+//	0x20202020,
+ //       0x20202020,
 //        0x20202020,
 //        0x20202020,
 //        0x20202020,
 //        0x20202020,
 //        0x20202020,
 };
-
+unsigned bus_type[256];

extern void get_sblk_pci1234(void);

static unsigned get_bus_conf_done = 0;

-static unsigned get_hcid(unsigned i)
-{
-        unsigned id = 0;
-
-        unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
-
-        unsigned devn = sysconf.hcdn[i] & 0xff;
-
-        device_t dev;
-
-        dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
-
-        switch (dev->device) {
-        case 0x0369: //IO55
-                id = 4;
-                break;
-        }
-
-        // we may need more way to find out hcid: subsystem id? GPIO read ?
-
-        // we need use id for 1. bus num, 2. mptable, 3. acpi table
-
-        return id;
-}
-
 void get_bus_conf(void)
 {

-       unsigned apicid_base;
-       struct mb_sysconf_t *m;
+	unsigned apicid_base;
+	unsigned sbdn;

device_t dev;
         int i, j;
@@ -105,11 +80,6 @@

get_bus_conf_done = 1;

-       sysconf.mb = &mb_sysconf;
-
-       m = sysconf.mb;
-       memset(m, 0, sizeof(struct mb_sysconf_t));
-
         sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
@@ -118,51 +88,59 @@

get_sblk_pci1234();

-       sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+	sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+	sbdn = sysconf.sbdn;

-       m->bus_type[0] = 1; //pci
+	for(i=0; i<8; i++) {
+		bus_mcp55[i] = 0;
+	}
+	
+	for(i=0;i<256; i++) {
+		bus_type[i] = 0;
+	}
+
+	bus_type[0] = 1; //pci
+	
+	bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;

-       m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+	bus_type[bus_mcp55[0]] = 1;

/* MCP55 */
-                dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
+                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06,0));
                 if (dev) {
-                        m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                        bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                        bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                        bus_mcp55[2]++;
+			for(j=bus_mcp55[1];j<bus_mcp55[2]; j++) bus_type[j] = 1;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
-                }
+                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);

-               for(i=2; i<8;i++) {
-                       dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
-                       if (dev) {
-                               m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                       }
-                       else {
-                               printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
-                       }
-               }
-
-       for(i=0; i< sysconf.hc_possible_num; i++) {
-               if(!(sysconf.pci1234[i] & 0x1) ) continue;
-
-                unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
-                unsigned busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
-               for (j = busn; j <= busn_max; j++)
-                       m->bus_type[j] = 1;
-               if(m->bus_isa <= busn_max)
-                       m->bus_isa = busn_max + 1;
-               printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
-       }
+                        bus_mcp55[1] = 2;
+                        bus_mcp55[2] = 3;
+                }

+		for(i=2; i<8;i++) {
+	                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0));
+        	        if (dev) {
+                	        bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	                        bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+        	                bus_isa++;
+				for(j=bus_mcp55[i];j<bus_isa; j++) bus_type[j] = 1;
+	                }
+        	        else {
+                	        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 );
+	                        bus_isa = bus_mcp55[i-1]+1;
+        	        }
+		}

-/*I/O APICs:   APIC ID Version State           Address*/
+/*I/O APICs:	APIC ID	Version	State		Address*/
 #if CONFIG_LOGICAL_CPUS==1
-       apicid_base = get_apicid_base(1);
-#else
-       apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+	apicid_base = get_apicid_base(1);
+#else 
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS; 
 #endif
-       m->apicid_mcp55 = apicid_base+0;
+	apicid_mcp55 = apicid_base+0;

}
diff -Naur ms9282/irq_tables.c ms7250/irq_tables.c
--- ms9282/irq_tables.c	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/irq_tables.c	2008-03-18 16:18:52.000000000 +0000
@@ -1,45 +1,46 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu  for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi  for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+/* This file was generated by getpir.c, do not modify!
+ * (but if you do, please run checkpir on it to verify)
  *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * Contains the IRQ Routing Table dumped directly from your
+ * memory, which BIOS sets up.
  *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
  */

-/* This file was generated by getpir.c, do not modify!
-   (but if you do, please run checkpir on it to verify)
-   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
-
-   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
+#ifdef GETPIR
+#include "pirq_routing.h"
+#else
+#include <arch/pirq_routing.h>
+#endif
 #include <console/console.h>
 #include <device/pci.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/pirq_routing.h>
+//#include <arch/pirq_routing.h>

#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
+
+
+
+/* Platform IRQs */
+#define PIRQA 10
+#define PIRQB 11
+#define PIRQC 10
+#define PIRQD 11
+
+#define PCI_DEV(BUS, DEV, FN) ( \
+	(((BUS) & 0xFF) << 16) | \
+	(((DEV) & 0x1f) << 11) | \
+	(((FN)  & 0x7) << 8))
+
+
+
+extern unsigned char bus_isa;
+extern unsigned char bus_mcp55[8]; //1

static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
-               uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
-               uint8_t slot, uint8_t rfu)
+  uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
+  uint8_t slot, uint8_t rfu)
 {
         pirq_info->bus = bus;
         pirq_info->devfn = devfn;
@@ -55,22 +56,65 @@
         pirq_info->rfu = rfu;
 }

-unsigned long write_pirq_routing_table(unsigned long addr)
+#if 0
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,  /* u32 signature */
+	PIRQ_VERSION,    /* u16 version   */
+	32+16*23,	 /* There can be total 23 devices on the bus */
+	0x00,		 /* Where the interrupt router lies (bus) */
+	(0x01<<3)|0x0,   /* Where the interrupt router lies (dev) */
+	0,		 /* IRQs devoted exclusively to PCI usage */
+	0x10de,		 /* Vendor */
+	0x364,		 /* Device */
+	0,		 /* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x46,		 /* u8 checksum. This has to be set to some
+			    value that would give 0 after the sum of all
+			    bytes for this structure (including checksum) */
+	{
+		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x01<<3)|0x0, {{0x02, 0x4ca0}, {0x05, 0x4ca0}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x02<<3)|0x0, {{0x08, 0x4ca0}, {0x03, 0x4ca0}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x08<<3)|0x0, {{0x0a, 0x4ca0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x09<<3)|0x0, {{0x09, 0x4ca0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x05<<3)|0x0, {{0x07, 0x4ca0}, {0x06, 0x4ca0}, {0x0f, 0x4ca0}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x06<<3)|0x0, {{0x00, 0x0000}, {0x0b, 0x4ca0}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x0f<<3)|0x0, {{0x85, 0x4ca0}, {0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x04ca0}}, 0x0, 0x0},
+		{0x07,(0x00<<3)|0x0, {{0x85, 0x4ca0}, {0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x04ca0}}, 0x20, 0x0},
+		{0x00,(0x0e<<3)|0x0, {{0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x4ca0}, {0x85, 0x04ca0}}, 0x0, 0x0},
+		{0x06,(0x00<<3)|0x0, {{0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x4ca0}, {0x85, 0x04ca0}}, 0x21, 0x0},
+		{0x00,(0x0d<<3)|0x0, {{0x87, 0x4ca0}, {0x84, 0x4ca0}, {0x85, 0x4ca0}, {0x86, 0x04ca0}}, 0x0, 0x0},
+		{0x05,(0x00<<3)|0x0, {{0x87, 0x4ca0}, {0x84, 0x4ca0}, {0x85, 0x4ca0}, {0x86, 0x04ca0}}, 0x22, 0x0},
+		{0x00,(0x0c<<3)|0x0, {{0x84, 0x4ca0}, {0x85, 0x4ca0}, {0x86, 0x4ca0}, {0x87, 0x04ca0}}, 0x0, 0x0},
+		{0x04,(0x00<<3)|0x0, {{0x84, 0x4ca0}, {0x85, 0x4ca0}, {0x86, 0x4ca0}, {0x87, 0x04ca0}}, 0x23, 0x0},
+		{0x00,(0x0b<<3)|0x0, {{0x85, 0x4ca0}, {0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x04ca0}}, 0x0, 0x0},
+		{0x03,(0x00<<3)|0x0, {{0x85, 0x4ca0}, {0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x04ca0}}, 0x24, 0x0},
+		{0x00,(0x0a<<3)|0x0, {{0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x4ca0}, {0x85, 0x04ca0}}, 0x0, 0x0},
+		{0x02,(0x00<<3)|0x0, {{0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x4ca0}, {0x85, 0x04ca0}}, 0x25, 0x0},
+		{0x01,(0x00<<3)|0x0, {{0x80, 0x4ca0}, {0x81, 0x4ca0}, {0x82, 0x4ca0}, {0x83, 0x04ca0}}, 0x1, 0x0},
+		{0x01,(0x01<<3)|0x0, {{0x81, 0x4ca0}, {0x82, 0x4ca0}, {0x83, 0x4ca0}, {0x80, 0x04ca0}}, 0x2, 0x0},
+		{0x01,(0x02<<3)|0x0, {{0x82, 0x4ca0}, {0x83, 0x4ca0}, {0x80, 0x4ca0}, {0x81, 0x04ca0}}, 0x3, 0x0},
+		{0x01,(0x05<<3)|0x0, {{0x82, 0x4ca0}, {0x83, 0x4ca0}, {0x80, 0x4ca0}, {0x81, 0x04ca0}}, 0x4, 0x0},
+		{0x01,(0x04<<3)|0x0, {{0x83, 0x4ca0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+	}
+};
+#endif
+
+
+unsigned long routing_table(unsigned long addr)
 {

-       struct irq_routing_table *pirq;
-       struct irq_info *pirq_info;
-       unsigned slot_num;
-       uint8_t *v;
-       struct mb_sysconf_t *m;
-       unsigned sbdn;
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ unsigned slot_num;
+ uint8_t *v;
+ unsigned sbdn;

uint8_t sum=0;
         int i;

get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
-       sbdn = sysconf.sbdn;
-       m = sysconf.mb;
+ sbdn = sysconf.sbdn;

/* Align the table to be 16 byte aligned. */
         addr += 15;
@@ -79,52 +123,408 @@
         /* This table must be betweeen 0xf0000 & 0x100000 */
         printk_info("Writing IRQ routing tables to 0x%x...", addr);

-       pirq = (void *)(addr);
-       v = (uint8_t *)(addr);
+ pirq = (void *)(addr);
+ v = (uint8_t *)(addr);
+ 
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version  = PIRQ_VERSION;
+ 
+ pirq->rtr_bus = bus_mcp55[0];
+ pirq->rtr_devfn = ((sbdn+1)<<3)|0;
+
+ pirq->exclusive_irqs = 0;
+ 
+ pirq->rtr_vendor = 0x10de;
+ pirq->rtr_device = 0x0360; //0x0370 0x0364;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *) ( &pirq->checksum + 1);
+ slot_num = 0;
+
+#if 0
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x01)<<3)|0, 0x2, 0x0800, 0x5, 0x0800, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x02)<<3)|0, 0x8, 0x4ca0, 0x3, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+// pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x08)<<3)|0, 0x0a, 0x0400, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x09)<<3)|0, 0x09, 0x0400, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x05)<<3)|0, 0x07, 0x0080, 0x6, 0x0400, 0x0f, 0x0800, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+# if 1 
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x06)<<3)|0, 0x00, 0x0000, 0x0b, 0x0020, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+# endif 
+
+# if 0 
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x00, 0x0000, 0x0b, 0xdef8, 0x00, 0x0000, 0x00, 0x0000, 0, 0);
+# endif 
+ 
+ pirq_info++; slot_num++;
+ // write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0f)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x07, ((sbdn+0x00)<<3)|0, 0x85, 0x0400, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x20, 0x0);
+ pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0e)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x06, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x21, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0d)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x05, ((sbdn+0x00)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x22, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0c)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x04, ((sbdn+0x00)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x23, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0b)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x03, ((sbdn+0x00)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x24, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0a)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x02, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x25, 0x0);
+// pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01, ((sbdn+0x00)<<3)|0, 0x80/*80*/, 0x0800, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x1, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01, ((sbdn+0x01)<<3)|0, 0x83/*81*/, 0x0800, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, /*0x2*/ 0x2, 0x0);
+ pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x01, ((sbdn+0x02)<<3)|0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x3, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x01, ((sbdn+0x05)<<3)|0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x4, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x01, ((sbdn+0x04)<<3)|0, 0x83, 0x0800, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+
+#endif
+
+
+
+#if 1 
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x01)<<3)|0, 0x2, 0x4ca0, 0x5, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x02)<<3)|0, 0x8, 0x4ca0, 0x3, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x08)<<3)|0, 0x0a, 0x4ca0, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x09)<<3)|0, 0x09, 0x4ca0, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x05)<<3)|0, 0x07, 0x4ca0, 0x6, 0x4ca0, 0x0f, 0x4ca0, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x06)<<3)|0, 0x00, 0x0000, 0x0b, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0f)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info,0x07 /*bus_mcp55[7]*/, ((sbdn+0x00)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x20, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0e)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x06 /*bus_mcp55[6]*/, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x21, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0d)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x05 /*bus_mcp55[5]*/, ((sbdn+0x00)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x22, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0c)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x04 /*bus_mcp55[0]*/, ((sbdn+0x00)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x23, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0b)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x03/*bus_mcp55[3]*/, ((sbdn+0x00)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x24, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0a)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x02/*bus_mcp55[2]*/, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x25, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[1]*/, ((sbdn+0x00)<<3)|0, 0x80, 0x4ca0, 0x81, 0x4ca0, 0x82, 0x4ca0, 0x83, 0x04ca0, 0x1, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x01)<<3)|0, 0x81, 0x4ca0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x04ca0, 0x2, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x02)<<3)|0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x3, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x05)<<3)|0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x4, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x04)<<3)|0, 0x83, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+#endif 
+ 
+ 
+ 
+ pirq->size = 32 + 16 * slot_num;
+
+        for (i = 0; i < pirq->size; i++)
+                sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+        if (sum != pirq->checksum) {
+                pirq->checksum = sum;
+        }

-       pirq->signature = PIRQ_SIGNATURE;
-       pirq->version  = PIRQ_VERSION;
+ printk_info("done.\n");
+
+ return (unsigned long) pirq_info;
+
+}

-       pirq->rtr_bus = m->bus_mcp55[0];
-       pirq->rtr_devfn = ((sbdn+6)<<3)|0;

-       pirq->exclusive_irqs = 0;

-       pirq->rtr_vendor = 0x10de;
-       pirq->rtr_device = 0x0370;

-       pirq->miniport_data = 0;

-       memset(pirq->rfu, 0, sizeof(pirq->rfu));

-       pirq_info = (void *) ( &pirq->checksum + 1);
-       slot_num = 0;
-//pci bridge
-       write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-       pirq_info++; slot_num++;
+unsigned long routing_table2(unsigned long addr)
+{

-        for(i=1; i< sysconf.hc_possible_num; i++) {
-                if(!(sysconf.pci1234[i] & 0x1) ) continue;
-                unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
-                unsigned devn = sysconf.hcdn[i] & 0xff;
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ unsigned slot_num;
+ uint8_t *v;
+ unsigned sbdn;

-                write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-                pirq_info++; slot_num++;
-       }
+        uint8_t sum=0;
+        int i;

-       pirq->size = 32 + 16 * slot_num;
+        get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+ sbdn = sysconf.sbdn;
+
+        /* Align the table to be 16 byte aligned. */
+        addr += 15;
+        addr &= ~15;
+
+        /* This table must be betweeen 0xf0000 & 0x100000 */
+        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+
+ pirq = (void *)(addr);
+ v = (uint8_t *)(addr);
+ 
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version  = PIRQ_VERSION;
+ 
+ pirq->rtr_bus = bus_mcp55[0];
+ pirq->rtr_devfn = ((sbdn+6/*+3*/)<<3)|0;
+
+ pirq->exclusive_irqs = 0;
+ 
+ pirq->rtr_vendor = 0x10de;
+ pirq->rtr_device = 0x0370; //0x0370; 0x0364
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *) ( &pirq->checksum + 1);
+ slot_num = 0;
+ 
+# if 1 /*from 7260*/
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x01, 0xdef8, 0x2,0xdef8 /*0x0020*/, 0x03, 0xdef8, 0x04, 0xdef8, 0x0, 0x0);
+ 
+ pirq_info++; slot_num++;
+# endif
+
+#if 1
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x01)<<3)|0, 0x2, 0x0800, 0x5, 0x0800, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x02)<<3)|0, 0x8, 0x4ca0, 0x3, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+// pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x08)<<3)|0, 0x0a, 0x0400, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x09)<<3)|0, 0x09, 0x0400, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x05)<<3)|0, 0x07, 0x0080, 0x6, 0x0400, 0x0f, 0x0800, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+# if 0 
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x06)<<3)|0, 0x00, 0x0000, 0x0b,0x0100 /*0x0020*/, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+# endif 
+
+# if 0 
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x00, 0x0000, 0x0b, 0xdef8, 0x00, 0x0000, 0x00, 0x0000, 0, 0);
+# endif 
+ 
+# if 0 /*from 7260*/
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x01, 0xdef8, 0x2,0xdef8 /*0x0020*/, 0x03, 0xdef8, 0x04, 0xdef8, 0x0, 0x0);
+ pirq_info++; slot_num++;
+# endif 
+
+ //pirq_info++; slot_num++;
+ 
+ // write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0f)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x07, ((sbdn+0x00)<<3)|0, 0x85, 0x0400, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x20, 0x0);
+ pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0e)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x06, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x21, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0d)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x05, ((sbdn+0x00)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x22, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0c)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x04, ((sbdn+0x00)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x23, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0b)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x03, ((sbdn+0x00)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x24, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0a)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x02, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x25, 0x0);
+// pirq_info++; slot_num++;
+
+ write_pirq_info(pirq_info, 0x01, ((sbdn+0x00)<<3)|0, 0x80/*80*/, 0x0800, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x1, 0x0);
+ pirq_info++; slot_num++;
+
+ write_pirq_info(pirq_info, 0x01, ((sbdn+0x01)<<3)|0, 0x81/*81*/,/*0x0800*/ 0x0800, 0x00,/*0x0*/ 0x0000, 0x00,/*0x0*/ 0x0000, 0x00, 0x00000, 0x2, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01, ((sbdn+0x02)<<3)|0, 0x82,/*0x4ca0*/  0x4c80, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x3, 0x0);
+ pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x01, ((sbdn+0x05)<<3)|0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x4, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x01, ((sbdn+0x04)<<3)|0, 0x83, 0x0800, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x0, 0x0);
+ //pirq_info++; slot_num++;
+
+#endif
+
+
+
+#if 0 
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x01)<<3)|0, 0x2, 0x4ca0, 0x5, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x02)<<3)|0, 0x8, 0x4ca0, 0x3, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x08)<<3)|0, 0x0a, 0x4ca0, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x09)<<3)|0, 0x09, 0x4ca0, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x05)<<3)|0, 0x07, 0x4ca0, 0x6, 0x4ca0, 0x0f, 0x4ca0, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x06)<<3)|0, 0x00, 0x0000, 0x0b, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0f)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info,0x07 /*bus_mcp55[7]*/, ((sbdn+0x00)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x20, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0e)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x06 /*bus_mcp55[6]*/, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x21, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0d)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x05 /*bus_mcp55[5]*/, ((sbdn+0x00)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x22, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0c)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x04 /*bus_mcp55[0]*/, ((sbdn+0x00)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x23, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0b)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x03/*bus_mcp55[3]*/, ((sbdn+0x00)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x24, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0a)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x02/*bus_mcp55[2]*/, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x25, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[1]*/, ((sbdn+0x00)<<3)|0, 0x80, 0x4ca0, 0x81, 0x4ca0, 0x82, 0x4ca0, 0x83, 0x04ca0, 0x1, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x01)<<3)|0, 0x81, 0x4ca0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x04ca0, 0x2, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x02)<<3)|0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x3, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x05)<<3)|0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x4, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x04)<<3)|0, 0x83, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+#endif 
+ 
+ 
+ 
+ pirq->size = 32 + 16 * slot_num;

for (i = 0; i < pirq->size; i++)
                 sum += v[i];

-       sum = pirq->checksum - sum;
+ sum = pirq->checksum - sum;

if (sum != pirq->checksum) {
                 pirq->checksum = sum;
         }

-       printk_info("done.\n");
+ printk_info("done.\n");

-       return  (unsigned long) pirq_info;
+ return (unsigned long) pirq_info;
+
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	int i, j, k, num_entries;
+	unsigned char pirq[4];
+	uint16_t chipset_irq_map;
+	uint32_t pciAddr, pirtable_end;
+	struct irq_routing_table *pirq_tbl;
+	unsigned functNum;
+	unsigned result;
+	device_t pdev;
+
+	//pirtable_end = copy_pirq_routing_table(addr);
+	pirtable_end = routing_table2(addr);
+
+	/* Set up chipset IRQ steering. */
+#if 0	
+/*just something I do not understand*/	
+	pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
+	chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
+	printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
+		     chipset_irq_map);
+	outl(pciAddr & ~3, 0xCF8);
+	outl(chipset_irq_map, 0xCFC);	
+#endif
+	pirq_tbl = (struct irq_routing_table *)(addr);
+	num_entries = (pirq_tbl->size - 32) / 16;
+
+	/* Set PCI IRQs. */
+	for (i = 0; i < num_entries; i++) {
+		//printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
+		//	     pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
+		for (j = 0; j < 4; j++) {
+			//printk_debug("INT: %c bitmap: %x ", 'A' + j,
+			//	     pirq_tbl->slots[i].irq[j].bitmap);
+			for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ;
+	/* Finds lsb in bitmap to IRQ#. */
+			pirq[j] = k;
+			//printk_debug("PIRQ: %d\n", k);
+		}
+
+		/* Bus, device, slots IRQs for {A,B,C,D}. */
+		pci_assign_irqs(pirq_tbl->slots[i].bus,
+				pirq_tbl->slots[i].devfn >> 3, pirq);
+	}
+	
+	for (functNum = 0; functNum < 8; functNum++) {
+		pdev = dev_find_slot(0x01, (0x01 << 3) + functNum);
+
+		if (pdev) {
+	
+	/*It was for realtek*/
+	//pdev = dev_find_slot(0x1, (0x1 << 3) + 0x0);
+	
+	//pci_write_config8(pdev, 0x55, 0x00);
+	/*
+	pci_write_config32(pdev, 0x55, 0xFFFFFFFF);
+	pci_write_config32(pdev, 0x55, 0x0);
+	printk_debug("0x55 Device found  \n");
+	result=pci_read_config8(pdev, 0x55);
+	print_debug_hex8(result);	*/
+	                     }
+	}
+	
+	//pirtable_end = routing_table(addr);

+	/* Put the PIR table in memory and checksum. */
+	return pirtable_end;
 }
diff -Naur ms9282/mainboard.c ms7250/mainboard.c
--- ms9282/mainboard.c	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/mainboard.c	2007-02-19 19:11:20.000000000 +0000
@@ -1,5 +1,5 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2006 MSI
  * Written by Bingxun Shi  for MSI.
diff -Naur ms9282/mb_sysconf.h ms7250/mb_sysconf.h
--- ms9282/mb_sysconf.h	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/mb_sysconf.h	2007-02-09 00:26:10.000000000 +0000
@@ -1,5 +1,5 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2006 AMD
  * Written by Yinghai Lu  for AMD.
diff -Naur ms9282/mptable.c ms7250/mptable.c
--- ms9282/mptable.c	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/mptable.c	2007-08-08 16:29:29.000000000 +0000
@@ -1,12 +1,9 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2006 AMD
+ * Copyright (C) 2007 AMD
  * Written by Yinghai Lu  for AMD.
  *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi  for MSI.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -29,19 +26,22 @@
 #include <stdint.h>

#include <cpu/amd/amdk8_sysconf.h>
+extern unsigned char bus_isa;
+extern unsigned char bus_mcp55[8]; //1
+
+extern unsigned apicid_mcp55;

-#include "mb_sysconf.h"
+extern unsigned bus_type[256];

void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
         static const char oem[8] = "MSI    ";
-        static const char productid[12] = "MS9282       ";
+        static const char productid[12] = "MS7250       ";
         struct mp_config_table *mc;
-       struct mb_sysconf_t *m;
-       unsigned sbdn;
+	unsigned sbdn;

-       int i,j;
+	int i,j;

mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
         memset(mc, 0, sizeof(*mc));
@@ -60,112 +60,145 @@
         mc->mpe_checksum = 0;
         mc->reserved = 0;

-        smp_write_processors(mc);
+       smp_write_processors(mc);
+       
+      // smp_write_processor(mc,0x00, 0x10,0x3, 0x0f32, 0x178bfbff);
+      // smp_write_processor(mc,0x01, 0x10,0x1, 0x0f32, 0x178bfbff);

-       get_bus_conf();
-       sbdn = sysconf.sbdn;
-       m = sysconf.mb;
+	get_bus_conf();
+	sbdn = sysconf.sbdn;

-/*Bus:         Bus ID  Type*/
+/*Bus:		Bus ID	Type*/
        /* define bus and isa numbers */
         for(j= 0; j < 256 ; j++) {
-               if(m->bus_type[j])
-                        smp_write_bus(mc, j, "PCI   ");
+		if(bus_type[j])
+			 smp_write_bus(mc, j, "PCI   ");
+			 
+			 
         }
-        smp_write_bus(mc, m->bus_isa, "ISA   ");
+        smp_write_bus(mc, bus_isa, "ISA   ");

-/*I/O APICs:   APIC ID Version State           Address*/
+/*I/O APICs:	APIC ID	Version	State		Address*/
         {
                 device_t dev;
-               struct resource *res;
-               uint32_t dword;
+		struct resource *res;
+		uint32_t dword;

-                dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
                 if (dev) {
-                       res = find_resource(dev, PCI_BASE_ADDRESS_1);
-                       if (res) {
-                               smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
-                       }
+			print_debug("Device found \r\n");
+			res = find_resource(dev, PCI_BASE_ADDRESS_1);
+			
+			
+			print_debug("PCI: ");
+			print_debug_hex32(dev);
+			
+			
+			if (res) {
+				smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
+				print_debug_hex32(res->base);
+				print_debug("\r\n");
+			}

-                       dword = 0x43c6c643;
-                       pci_write_config32(dev, 0x7c, dword);
+			dword = 0x43c6c643;
+	        	pci_write_config32(dev, 0x7c, dword);

-                       dword = 0x81001a00;
-                       pci_write_config32(dev, 0x80, dword);
+		        dword = 0x81001a00;
+		        pci_write_config32(dev, 0x80, dword);

-                       dword = 0xd00002d2;
-                       pci_write_config32(dev, 0x84, dword);
+	        	dword = 0xd0001202;
+		        pci_write_config32(dev, 0x84, dword);

}
-
-
-       }
-
-                  /*I/O Ints:  Type    Polarity    Trigger                     Bus ID   IRQ    APIC ID PIN# */
-       smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x3, m->apicid_mcp55, 0x3);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x4, m->apicid_mcp55, 0x4);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x6, m->apicid_mcp55, 0x6);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x7, m->apicid_mcp55, 0x7);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x8, m->apicid_mcp55, 0x8);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xc, m->apicid_mcp55, 0xc);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xd, m->apicid_mcp55, 0xd);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
-
-//SMBUS
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
-
-//USB1.1
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
-
-//USB2.0
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
-
-//SATA1
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
-
-//SATA2
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
-
-//SATA3
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
-
-//NIC1
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
-//NIC2
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
-
-       for(j=7; j>=2; j--) {
-               if(!m->bus_mcp55[j]) continue;
-               for(i=0;i<4;i++) {
-                       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
-               }
-       }
-
-       for(j=0; j<1; j++)
-               for(i=0;i<4;i++) {
-                       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
-               }
-
-/*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
-       smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
-       smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
-       /* There is no extension information... */
-
-       /* Compute the checksums */
-       mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-       mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-       printk_debug("Wrote the mp table end at: %p - %p\n",
-               mc, smp_next_mpe_entry(mc));
-       return smp_next_mpe_entry(mc);
+	}
+  
+/*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
+*/
+	//apicid_mcp55=0x0;
+	print_debug("bus_isa "); print_debug_hex32(bus_isa); print_debug("\r\n");
+	print_debug("bus_mcp55[0] "); print_debug_hex32(bus_mcp55[0]); print_debug("\r\n");
+	print_debug("bus_mcp55[1] "); print_debug_hex32(bus_mcp55[1]); print_debug("\r\n");
+	print_debug("apicid_mcp55 "); print_debug_hex32(apicid_mcp55); print_debug("\r\n");
+	//print_debug("(sbdn+8)<<2)"); print_debug_hex32((sbdn+8)<<2)); print_debug("\r\n");
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_mcp55, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, apicid_mcp55, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, apicid_mcp55, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, apicid_mcp55, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, apicid_mcp55, 0x6);
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH,  bus_mcp55[1], 0x5, apicid_mcp55, 0x5);
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, apicid_mcp55, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, apicid_mcp55, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid_mcp55, 0x9);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, apicid_mcp55, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, apicid_mcp55, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, apicid_mcp55, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_mcp55, 0xf);
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|0/*1*/, apicid_mcp55, 0xb/*0xa*/);
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, /*0x15*/0x5); // 23 0X17
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, /*0x14*/0x07); // 20
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, /*0x17*/0x05); // 23
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, /*0x15*/0xb); // 21
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, /*0x16*/0xa); // 22
+	
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, /*0x16*/0xa); // 22 new device
+	
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x07/*bus_mcp55[7]*/, ((sbdn+0)<<2)|0, apicid_mcp55, /*0x16*/0xa);//new device
+	
+	/*ethernet 0 */
+#if 0	
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x01/*bus_mcp55[1]*/, ((sbdn+1)<<2)|0, apicid_mcp55, 0xb); // 12
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_LOW, bus_mcp55[1], 0x0, ((sbdn+1)<<2)|0, 0x5); // 5
+	/*smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((sbdn+1)<<2)|1, apicid_mcp55, 0xc); // 5*/
+# endif	
+	
+#if 1/*Test version do not destribute interrupts */
+	for(j=7; j>=2; j--) {
+		if(!bus_mcp55[j]) continue;
+	        for(i=0;i<4;i++) {
+        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+        	}
+	}
+
+	for(j=0; j<2; j++) 
+	        for(i=0;i<4;i++) {
+        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x00+j)<<2)|i, apicid_mcp55, 0x05 + (2+i+j)%4);
+	        }
+		
+#endif		
+		//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((sbdn+1)<<2)|0, apicid_mcp55, 0x); // 22
+	
+
+/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	
+	/* Compute the checksums */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	
+	
+	
+	
+	
+	printk_debug("Wrote the mp table end at: %p - %p\n",
+		mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
 }

unsigned long write_smp_table(unsigned long addr)
 {
-       void *v;
-       v = smp_write_floating_table(addr);
-       return (unsigned long)smp_write_config_table(v);
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
 }
diff -Naur ms9282/resourcemap.c ms7250/resourcemap.c
--- ms9282/resourcemap.c	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/resourcemap.c	2007-07-05 16:24:30.000000000 +0000
@@ -1,5 +1,5 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2003 Stefan Reinauer 
  *

[Stefan Reinauer]

George V. Adamov wrote:
> finally there is a patch which makes src/mainboard/msi/ms7250 from
> src/mainboard/msi/ms9285 (I used the most current version 3241 for
> ms9285).
>
> I hope we will make ms7250 workable completely and place it to the
> coreboot tree ))))

Hi,

thanks a lot for your patch!

Could you please clean it up against the latest svn tree? Your patch
renames all occurences of coreboot to LinuxBIOS.

Stefan

[yhlu]

On Fri, Apr 11, 2008 at 5:27 AM, George V. Adamov  wrote:
> yhlu wrote:

...
> I boot 2.4.21 kernel it works fine under stock BIOS is there any chance to
> make this kernel work under LinuxBIOS?

not tested that. please check using 64 bit and smp enable config.

YH